Memory Access Control Circuitry for Multi-Rank Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Accessing large amounts of data in memory efficiently is challenging due to timing restrictions and high power requirements, especially when dealing with multiple memory units or ranks, which necessitates careful tracking and control to avoid violating individual unit properties and reduce latency and area costs.
Innovation Solution
A memory access circuitry with two access units, each configured to select and track multiple memory units, using arbitration and tracking circuitry to manage access requests, store them in queues, and switch states periodically to optimize access and activation requests, allowing for efficient interleave and power management without excessive latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-rank DRAM is used to increase accessing speeds, then memory access throughput is improved, but switching between ranks incurs additional costs and complexity
Solution Approach 1:
The memory system is divided into multiple ranks, each with its own access unit and tracking circuitry. This segmentation allows parallel access to different memory units, improving throughput while distributing the tracking complexity across multiple independent units rather than requiring a single complex controller.
Solution Approach 2:
The tracking circuitry proactively monitors and records access patterns and timing for each memory unit before conflicts occur. By maintaining ready-to-use tracking information in advance, the system can quickly switch between ranks without incurring additional latency or control complexity when access patterns change.
2Reliability
If tracker devices are provided for each memory unit to track accesses, then individual unit properties are protected, but device area increases significantly
Solution Approach 1:
Instead of implementing complex tracking logic in each access unit, the patent uses simplified tracking circuitry that copies and maintains essential timing and access state information. This copying approach provides the necessary tracking capability to enforce memory timing constraints while using significantly less area than full tracking devices for each memory unit.
3Productivity
If activate commands are issued frequently to increase access speed, then memory throughput improves, but timing restrictions and power consumption increase
Solution Approach 1:
The tracking circuitry continuously monitors the state of each memory unit and provides feedback to the access units about which units are ready to accept activate commands. This feedback mechanism allows the system to issue activate commands at the optimal frequency, maximizing throughput while avoiding excessive power consumption from issuing commands too frequently to units that are not ready.
Data Source
AI summary
Memory access circuitry controls access to multiple memory units with two access units. Arbitration circuitry forwards memory access requests for one memory unit to a first access unit, for a further memory unit to a second access unit, and for yet further memory unit to one of the first or second access units. The access units store requests in a queue prior to transmitting them to the respective memory unit. Tracking circuitry tracks requests and determines when to transmit subsequent requests from the queue. Control circuitry sets a state of each access unit to one of active, prepare and dormant, switches states of the two access units periodically, and does not set more than one access unit to the active state at the same time.