Memory Adapter Compression for Main Memory Capacity Scaling
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Solution Overview
Problem
Modern applications with large main memory footprints face increasing storage capacity needs that scale super-linearly, necessitating a system to enhance memory capacity efficiently.
Innovation Solution
A pseudo main memory system employing a memory adapter circuit for compression, deduplication, and error correction, connected to a memory bus and utilizing a non-volatile dual in-line memory module with flash memory interface, to augment storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased to meet growing application needs, then storage capacity is improved, but system cost and physical footprint increase
Solution Approach 1:
The patent combines multiple memory devices with different characteristics (overprovisioned memory devices with lower density and higher capacity devices) into a unified memory system. The memory adapter circuit integrates these diverse devices, allowing them to function together as a single logical memory unit, thereby increasing total capacity without proportionally increasing system complexity or cost.
Solution Approach 2:
The memory adapter circuit performs multiple functions: it manages data distribution across different memory devices, handles error correction, and provides a unified interface to the host system. This multi-functionality allows the system to achieve greater capacity while using a single adapter circuit rather than requiring separate control logic for each memory device.
2Area of stationary object
If memory density is increased to reduce physical footprint, then area is improved, but access speed and reliability may deteriorate
Solution Approach 1:
The patent applies different memory devices with locally optimized characteristics to different parts of the memory address space. Overprovisioned devices are used for certain regions while higher density devices are used for others, allowing each region to be accessed through its most suitable physical medium while maintaining a compact overall footprint.
Solution Approach 2:
The memory adapter circuit acts as an intermediary between the host system and the diverse memory devices. It transparently handles access requests, translating them to the appropriate physical devices and managing data movement between them. This intermediary layer maintains reliability and access speed by optimizing data paths while enabling the use of high-density storage.
3Quantity of substance
If memory capacity is scaled to accommodate large applications, then storage capacity is improved, but access latency increases
Solution Approach 1:
The patent divides the large memory capacity into segments managed by different physical devices. The memory adapter circuit segments the address space and distributes access requests to appropriate devices based on the data location. This segmentation allows parallel access to different memory regions, reducing overall access latency even as total capacity increases.
Solution Approach 2:
The system pre-positions data in the memory hierarchy by moving frequently accessed data to faster memory devices and less frequently accessed data to higher capacity devices. The memory adapter circuit monitors access patterns and performs preliminary data movement to optimize future access latency, ensuring that hot data is readily available even in a large-capacity system.
Data Source
AI summary
A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.