Memory Device Adaptive Program Limit Voltage Control
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Solution Overview
Problem
Current memory devices face inefficiencies in programming operations due to repetitive program loops and lack of optimized voltage application methods, leading to suboptimal performance and speed.
Innovation Solution
A memory device with a peripheral circuit and control logic that performs multiple program loops with adaptive voltage application based on cell status information, allowing for reduced program time by omitting verify operations in certain loops and applying program limit voltages to bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple program loops are performed with verify operations in each loop, then the threshold voltage of memory cells can be accurately controlled to reach the target threshold voltage, but the programming time is extended due to repetitive verify operations
Solution Approach 1:
The patent applies preliminary action by performing a verify operation in advance (in the N-2 th program loop) before the actual target threshold voltage verification is needed. This early verify operation allows the system to predict whether the threshold voltage will reach the target in the Nth program loop, enabling the omission of intermediate verify operations in the (N-1)th program loop while still ensuring accurate threshold voltage control.
2Reliability
If verify operations are performed in every program loop, then the programming operation can be completed with reliable threshold voltage verification, but the overall programming speed is reduced due to repetitive operations
Solution Approach 1:
The patent implements feedback by using the verify pass signal obtained in the N-2 th program loop to control subsequent programming operations. This feedback mechanism allows the system to make informed decisions about whether to continue programming without performing redundant verify operations, thereby maintaining reliability while improving programming speed.
Solution Approach 2:
The verify operation performed in the N-2 th program loop serves as a preliminary action that provides advance information about the programming status. This preliminary verification enables the system to skip unnecessary verify operations in intermediate loops while ensuring that the final threshold voltage target is reliably achieved.
3Ease of operation
If uniform programming voltage is applied to all bit lines, then the programming operation is simple to control, but the programming efficiency is suboptimal due to lack of adaptive voltage application
Solution Approach 1:
The patent applies local quality by differentiating the programming voltage application across different bit lines based on cell status information. Instead of using a uniform voltage for all bit lines, the system applies program limit voltages selectively to bit lines where memory cells require additional programming, thereby improving programming efficiency without complicating the overall control mechanism.
Solution Approach 2:
The patent implements dynamics by making the programming voltage adaptive rather than static. The program limit voltage applied to each bit line is dynamically determined based on cell status information from previous verify operations, allowing the system to adjust voltage application in real-time according to the actual programming needs of different memory cell groups.
Data Source
AI summary
A memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes memory cells. The peripheral circuit performs a program operation including a plurality of program loops. Each of the plurality of program loops includes a program pulse application operation and a verify operation. The control logic controls the peripheral circuit to store cell status information and apply a program limit voltage. The control logic sets a verify pass reference and applies the program limit voltage determined based on the cell status information.