Memory Address Remapping for Double-Bit Error Correction
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Solution Overview
Problem
Existing error correction schemes fail to correct double-bit errors in memory devices, leading to data corruption and requiring module replacement, as they cannot effectively manage errors occurring at the same address.
Innovation Solution
Transforming the addresses of memory devices with double-bit errors to remap them into correctable single-bit errors by accessing different internal memory cells, thereby reducing the number of erroneous bits to a manageable level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing error correction schemes are used, then single-bit errors can be corrected, but double-bit errors cannot be corrected leading to data corruption
Solution Approach 1:
The patent segments the address space by maintaining two separate address mappings: original addresses and transformed addresses. When a double-bit error is detected at a given address, the system switches to using transformed addresses for that specific memory location, effectively segmenting the error handling approach by address rather than requiring complex correction for all addresses uniformly.
Solution Approach 2:
The patent transforms address parameters by applying a transformation function to map original addresses to transformed addresses. This parameter change allows the same physical memory cell to be accessed through different address representations, enabling the system to bypass erroneous address-bit combinations that cause double-bit errors.
2Reliability
If memory modules are replaced to prevent data corruption, then reliability is maintained, but loss of time and increased cost occur
Solution Approach 1:
The patent implements preliminary error detection and address transformation setup during system initialization or when errors are first detected. By pre-configuring the address transformation mappings and detecting errors before they cause data corruption, the system avoids the need for time-consuming module replacement operations.
Solution Approach 2:
The patent converts the harmful effect of double-bit errors into a beneficial outcome by using the error detection information to switch to transformed addresses. The erroneous address patterns that would normally cause data corruption are instead used to trigger the address transformation mechanism, turning the error condition into a signal for activating the remapping solution.
3Reliability
If address transformation is applied to all memory devices, then double-bit errors are converted to correctable single-bit errors, but device complexity increases
Solution Approach 1:
The patent applies address transformation selectively rather than uniformly across all memory devices. The transformation is applied only to specific memory addresses where double-bit errors have been detected, while other addresses continue to use the original address mapping. This localized approach reduces the overall complexity compared to transforming all addresses.
Solution Approach 2:
The patent introduces an intermediary address transformation layer that sits between the controller and memory devices. This intermediary component handles the complexity of address transformation, mapping original addresses to transformed addresses only when needed, thereby isolating the complexity from the memory devices themselves and the controller logic.
Data Source
AI summary
Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.