Semiconductor Memory Address Inversion for Near-Cell Error Compensation
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Solution Overview
Problem
Semiconductor memory devices with cross-point arrays using phase changeable materials experience high bit error rates in near cell regions, leading to low test yield due to differences in signal transmission characteristics between near and far cells.
Innovation Solution
A semiconductor system with control blocks that generate internal addresses for selecting memory cells, where one set of semiconductor devices receives a first internal address corresponding to an external address and another set receives a second internal address that inverts the first, effectively reducing bit error rates by compensating error frequencies between near and far cell regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If error test process is performed on near cell region, then error ratio in near cell region is greatly increased, but test yield of semiconductor chip is reduced
Solution Approach 1:
The patent applies address inversion technique where the address input to a second memory device is the inverted version of the address input to a first memory device. This causes memory cells at symmetric positions relative to control blocks to be accessed simultaneously, thereby distributing error concentrations and preventing instantaneous error ratio spikes that would reduce test yield.
Solution Approach 2:
The patent changes the address parameter by inverting it (using inverted addresses for different memory devices) to transform the error distribution pattern. This parameter transformation converts concentrated errors in near-cell regions into distributed errors across multiple regions, resolving the contradiction between error detection accuracy and test yield.
2Reliability
If near cell region is tested, then error ratio increases due to signal transmission characteristics, but this leads to low chip yield
Solution Approach 1:
By inverting addresses for second memory devices, the patent ensures that when near-cell regions of first devices are tested (where errors occur), corresponding far-cell regions of second devices are tested simultaneously. This inversion strategy balances error concentrations and maintains high chip yield while preserving error detection capability.
Solution Approach 2:
The patent merges the testing of near-cell and far-cell regions by simultaneously accessing memory cells at symmetric positions across different memory devices using inverted addresses. This combination allows error detection in near-cell regions without sacrificing chip yield, as errors are distributed across the merged test set.
3Adaptability or versatility
If control blocks are arranged at boundaries between memory cell arrays, then separate control is enabled, but signal transmission differences cause bit errors in near cell region
Solution Approach 1:
The patent uses address inversion to compensate for the reliability issue caused by control block placement. By inverting addresses for second memory devices, memory cells at symmetric positions (one near control block, one far from control block) are accessed together, balancing out the bit errors caused by signal transmission differences and maintaining overall system reliability.
Data Source
AI summary
A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.