Memory Address Table Synchronization for Low-Power High-Bandwidth Access
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Solution Overview
Problem
Memory devices face challenges in providing high data storage capacity and bandwidth while minimizing standby power consumption, particularly due to the inefficiencies in clock domain separation and gapless data communication in configurations with high-frequency data buses and low-frequency command buses.
Innovation Solution
The implementation of a memory device with a command/address decoder that includes a buffer memory and decoding logic circuits to synchronize with a memory controller, enabling the storage and utilization of an address table for improved command and address decryption, along with a scheduler to generate and encode sub-tables for efficient table synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If increased operating frequency is used to provide high data storage capacity and bandwidth, then data capacity and bandwidth are improved, but standby power consumption increases
Solution Approach 1:
The patent implements dynamic frequency adjustment where the memory device operates at high frequency during active data transfer to ensure high bandwidth, and transitions to low frequency or standby mode during idle periods to reduce power consumption. The command/address decoder dynamically synchronizes with the memory controller's timing requirements, adjusting its operating characteristics based on whether data is being transferred or the device is in standby state.
2Use of energy by moving object
If clock domain separation is introduced to reduce standby power consumption, then power consumption is reduced, but gapless data communication becomes impossible
Solution Approach 1:
The command/address decoder serves as an intermediary component that bridges the memory controller's command bus and the memory device's internal high-speed data bus. It translates and synchronizes commands from the controller's clock domain with the memory device's internal operations, enabling seamless data transfer across clock domain boundaries while maintaining gapless communication.
Solution Approach 2:
The command/address decoder preliminarily processes and synchronizes command/address information before it reaches the memory array, preparing data transfer operations in advance. This preliminary synchronization ensures that when data transfer is initiated, the high-frequency data bus is already ready to operate without gaps, even though the command bus operates at lower frequency during standby periods.
3Use of energy by moving object
If high-frequency data bus and low-frequency command bus are used, then standby power consumption is reduced, but bandwidth shortage occurs in transferring commands and addresses
Solution Approach 1:
The patent segments the command transfer process into efficient batches using address table synchronization. Instead of transferring individual commands sequentially at low frequency, the system synchronizes address tables in advance, allowing multiple commands to be processed efficiently using the high-frequency data bus for address table transfer, while the command bus operates at lower frequency for actual command issuance.
Data Source
AI summary
A memory device includes; a memory cell array, and a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table. The command/address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.