Nonvolatile Memory Read Method Using Aggressor Cell Precharging
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Solution Overview
Problem
NAND-type flash memory devices face challenges in reading data due to electrical interference from adjacent cells, which causes threshold voltage shifts and reduces read speed and accuracy, especially as integration density increases.
Innovation Solution
The method involves identifying adjacent memory cells as aggressor or non-aggressor cells based on their data states, selectively precharging bitlines, and using different read voltages to address interference, with a page buffer and control logic managing the precharging and sensing operations to improve read accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration density of memory cells is increased, then storage capacity is improved, but electrical interference from adjacent cells increases causing threshold voltage shifts and reduced read accuracy
Solution Approach 1:
The patent segments the memory cell array into multiple blocks, with each block containing selected memory cells and their adjacent memory cells. This segmentation allows independent sensing operations for each block, enabling selective precharging of bitlines based on the data states of adjacent cells without affecting other blocks. The segmentation isolates interference effects to local blocks while maintaining overall high-density storage capacity.
Solution Approach 2:
The patent performs preliminary sensing of adjacent memory cells before sensing the selected memory cells. Based on the data states of adjacent cells (aggressor or non-aggressor), the system precharges bitlines in advance before reading the selected cells. This preliminary action compensates for electrical interference by establishing appropriate bitline voltage levels before the actual read operation, thereby maintaining read accuracy in high-density configurations.
2Speed
If adjacent memory cells are sensed simultaneously with selected memory cells, then read speed is improved, but electrical interference causes threshold voltage shifts and sensing errors
Solution Approach 1:
The patent performs preliminary sensing of adjacent memory cells before sensing the selected memory cells. This preliminary action determines the data states of adjacent cells (whether they are aggressor or non-aggressor cells) so that appropriate precharging can be applied to bitlines before the actual read operation. This sequence maintains reliability by compensating for interference effects before they occur during simultaneous sensing.
Solution Approach 2:
The patent applies different precharging strategies to different bitlines based on the local data states of adjacent cells. Bitlines connected to selected memory cells adjacent to aggressor cells receive different precharging treatment compared to bitlines connected to selected memory cells adjacent to non-aggressor cells. This local quality approach allows simultaneous sensing operations while maintaining sensing accuracy by tailoring the read operation to local interference conditions.
3Device complexity
If bitlines are precharged uniformly for all selected memory cells, then device complexity is reduced, but read accuracy decreases due to varying electrical interference from adjacent cells
Solution Approach 1:
The patent segments the memory array into multiple blocks, with each block independently processed. Within each block, the system identifies and categorizes adjacent cells as aggressor or non-aggressor based on their data states. This segmentation enables selective precharging of bitlines within each block while maintaining a relatively simple overall control structure that can be replicated across blocks.
Solution Approach 2:
The patent implements local quality by applying different precharging voltages or timing to bitlines based on the specific data states of adjacent cells. The control logic determines whether each adjacent cell is an aggressor or non-aggressor and accordingly adjusts the precharging operation for the associated bitline. This localized adaptation maintains high read accuracy without requiring a completely complex control system, as the same control logic can be reused across multiple blocks.
Data Source
AI summary
A method of reading a nonvolatile memory device comprises sensing data stored in memory cells adjacent to selected memory cells to identify adjacent aggressor cells, and performing separate precharge operations on bitlines connected to selected memory cells having adjacent aggressor cells and on bitlines connected to selected memory cells having adjacent non-aggressor cells.