Memory Array Testing via Address Mask Lines for Parallel Write Operations
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Solution Overview
Problem
Current test methods for non-volatile memory devices are time-consuming, especially for large EEPROMs, as they require multiple write operations to check for defects like shorts between lines, which significantly increases the test time and production costs.
Innovation Solution
The introduction of additional address mask input lines allows for parallel writing of test patterns across multiple rows, reducing the number of write operations needed and enabling efficient testing by ignoring specific address bits, thereby speeding up the testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional write operations are used to test each row individually, then testing accuracy is improved, but test time increases significantly
Solution Approach 1:
The address bus is segmented into two independent parts: a functional address bus for selecting specific rows, and a test address bus with mask lines for selecting groups of rows simultaneously. This segmentation allows the system to perform both individual row testing and parallel group testing, resolving the contradiction between testing accuracy and test time by enabling different testing strategies for different test objectives.
Solution Approach 2:
The patent adds a new dimension to the address selection mechanism by introducing mask lines that operate independently from the traditional address bus. This creates a two-dimensional address selection space where rows can be selected both by their address and by their mask state, enabling parallel testing of multiple rows without compromising the ability to test individual rows when needed.
2Reliability
If multiple write operations are performed to check for shorts between lines, then defect detection capability is improved, but productivity decreases
Solution Approach 1:
Multiple row selections are merged into a single write operation by activating multiple mask lines simultaneously. Instead of performing separate write operations for each row or group of rows, the mask mechanism allows multiple rows to be selected and tested in parallel within a single write cycle, thereby improving productivity while maintaining comprehensive defect detection capability.
Solution Approach 2:
The mask lines remain active during the write operation, maintaining continuous selection of the target rows throughout the entire write cycle. This ensures that the useful action of writing test patterns continues uninterrupted across multiple rows simultaneously, maximizing testing throughput without sacrificing defect detection reliability.
3Loss of time
If address mask input lines are added to enable parallel writing, then test time is reduced, but device complexity increases
Solution Approach 1:
The mask lines are designed to serve multiple functions: they can be used for parallel row selection during testing, for group erasure operations, and for implementing various testing algorithms. This multi-functionality justifies the added complexity by providing a versatile tool that benefits multiple operations beyond just reducing test time, thereby resolving the contradiction between test time reduction and device complexity.
Data Source
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Figure 2a~2b
Figure 3
AI summary
The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines (addr_in_0, addr_in_1, ...) for selecting a row according to a particular address given on the address input lines. Additional address mask input lines (addr_msk_0, addr_msk_1, ...) are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line (addr_in_0, addr_in_1, ...). The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.