3D Memory Array Air Gaps for Lower Bit-Line Capacitance
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in reducing parasitic capacitance between bit lines and source lines, which limits the frequency operation and efficiency of memory devices.
Innovation Solution
A 3D memory array is designed with vertically stacked memory cells, incorporating air gaps between bit lines and source lines to reduce capacitance, formed by trenching and sealing with insulating material, and using an oxide semiconductor channel region with a ferroelectric memory film for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor memory structures are used with solid dielectric materials between bit lines and source lines, then structural stability is maintained, but parasitic capacitance is high which limits frequency operation
Solution Approach 1:
The patent changes the dielectric parameter by replacing solid dielectric materials with air gaps (vacuum), which have significantly lower dielectric constants. This parameter change directly reduces parasitic capacitance between bit lines and source lines, enabling higher frequency operation of the memory device.
Solution Approach 2:
The patent introduces air gaps (porous structure) between bit lines and source lines instead of using solid dielectric materials. These air gaps act as low-k dielectric regions that reduce parasitic capacitance while maintaining the necessary electrical isolation, thereby improving frequency operation.
2Speed
If air gaps are introduced to reduce parasitic capacitance, then frequency operation improves, but device complexity increases due to additional trenching and sealing processes
Solution Approach 1:
The patent segments the dielectric region into multiple parts: solid dielectric material in the main interconnect region and air gaps in specific regions between bit lines and source lines. This segmentation allows the device to maintain structural stability where needed while reducing parasitic capacitance where required, balancing performance improvement with manageable complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables higher-frequency operation and improved device efficiency by minimizing parasitic capacitance and enhancing read/write operations in memory arrays.
Implementation Method 1
isolation regions, wherein each isolation region is between a source line and a bit line... By separating the bit lines and source lines with air gaps, capacitance between the bit lines and source lines can be reduced
Implementation Method 2
each of the isolation regions includes an air gap and a seal extending over the air gap
Data Source
AI summary
A device includes a semiconductor substrate; a word line extending over the semiconductor substrate; a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; source lines extending along the memory film, wherein the memory film is between the source lines and the word line; bit lines extending along the memory film, wherein the memory film is between the bit lines and the word line; and isolation regions, wherein each isolation region is between a source line and a bit line, wherein each of the isolation regions includes an air gap and a seal extending over the air gap.