Memory Array Byte Accessibility Without Select Transistors
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Solution Overview
Problem
Conventional EEPROM memory devices require dedicated byte select transistors for byte accessibility, which occupy significant silicon space and add complexity, making it challenging to increase memory array density while maintaining simplicity and maturity of device structure and manufacturing process.
Innovation Solution
The proposed memory device eliminates individual byte select transistors by using a matrix of memory cells with page and source control devices, allowing byte accessibility through voltage combinations applied to external pins, reducing the number of control devices and eliminating the need for well biasing or isolation, thereby increasing density and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If dedicated byte select transistors are used for byte accessibility, then byte accessibility is achieved, but silicon area is significantly occupied
Solution Approach 1:
The invention extracts and removes the dedicated byte select transistors from the memory array structure. Instead of having individual byte select transistors for each byte, the patent eliminates these transistors entirely and achieves byte accessibility through a different mechanism using page select transistors and column select lines, thereby freeing up significant silicon area while maintaining byte-level access capability
Solution Approach 2:
The page select transistors are designed to serve multiple functions: they act as both page selection devices and byte selection devices. By controlling the word line voltages and column select lines in different combinations, the same page select transistor structure enables both page-wide access and individual byte access, eliminating the need for separate dedicated byte select transistors
2Quantity of substance
If well isolation structures are implemented to eliminate byte select transistors, then device density is increased, but process complexity and manufacturing steps are added
Solution Approach 1:
The invention removes the well isolation structures (such as deep trenches or triple wells) that were previously necessary to enable byte accessibility without dedicated byte select transistors. The patent achieves byte accessibility through voltage control of existing structures (page select transistors and column select lines) rather than through physical isolation, thereby simplifying the manufacturing process while maintaining high device density
Solution Approach 2:
The patent changes the operational parameters (voltage levels and timing) of the existing memory structures to achieve byte accessibility. By applying specific voltages to word lines and column select lines in different sequences, the invention enables byte-level access without requiring physical isolation structures, thus avoiding additional manufacturing complexity
3Area of stationary object
If byte select transistors are eliminated to increase density, then silicon area is reduced, but device complexity increases due to complex biasing schemes
Solution Approach 1:
The patent designs the page select transistors to perform multiple selection functions. The same transistor structure is used for both page selection and byte selection by varying the control signals on word lines and column select lines. This multi-functionality reduces silicon area while avoiding the need for complex additional biasing schemes that would increase device complexity
Data Source
AI summary
A memory device comprises at least one memory array on a semiconductor substrate. Each said memory array comprises a page control line and a plurality of pages, each said page is arranged in a row comprising a plurality of bytes which couple to a page control transistor with its drain terminal connected to the page control line. Each said byte includes at least one memory cell. Said memory array further comprises a plurality of source control devices which are configured to provide either predetermined biases or floating potentials to source lines, each said source line couples to all the bytes on the same byte segment of the memory array. Read, erase, and program methods are provided to operate said memory devices in byte addressable fashion.