Memory Array Layout for Byte Erase With Shared Wells
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Solution Overview
Problem
Existing nonvolatile memory arrays face challenges in reducing circuit area and efficiently performing byte operations due to the need for isolated memory cells and complex control signals, which increases the circuit area and complicates signal control.
Innovation Solution
The memory array design includes memory pages with memory bytes that share erase lines and control lines, allowing for independent control of memory bytes within a page while reducing circuit area by sharing wells and active regions, enabling efficient byte program and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If memory cells are disposed in isolated regions to enable independent control, then independent operation of memory cells is achieved, but circuit area significantly increases
Solution Approach 1:
The patent merges multiple memory bytes into a shared well region, allowing them to share common bias lines (source line, bit line, control line) while maintaining independent control through individual word lines. This consolidation eliminates the need for separate isolated regions for each memory byte, significantly reducing circuit area while preserving independent operation capability.
Solution Approach 2:
The shared well region serves multiple functions: it provides common source and bit lines for multiple memory bytes, shares control lines for efficient signal distribution, and enables both byte-program and byte-erase operations through the same physical infrastructure. This multi-functionality reduces the overall circuit area required compared to dedicated isolated regions.
2Adaptability or versatility
If byte operations are implemented to meet system requirements, then system functionality is improved, but control signal complexity increases
Solution Approach 1:
The memory array is segmented into multiple independently controllable memory bytes within a shared well. Each memory byte can be selectively accessed and operated on independently through its dedicated word line, while sharing common source, bit, and control lines. This segmentation enables byte-level operations without requiring separate physical isolation for each byte.
Solution Approach 2:
The patent implements dynamic control of memory bytes through selective word line activation. Different memory bytes can be programmed or erased simultaneously or independently by activating specific word lines, allowing flexible byte operations. The shared well region dynamically responds to control signals applied to different word lines, enabling versatile byte-level operations.
Data Source
AI summary
A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible.