Memory Array Conductive Tiers With Doped Semiconductor Coupling

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Solution Overview

Problem

Current memory array fabrication methods face challenges in minimizing undesired etching and ensuring precise electrical coupling between channel material strings and conductor tiers, which can affect the reliability and efficiency of memory cell formation.

Innovation Solution

The method involves forming a conductor tier on a substrate with laterally-spaced memory-block regions comprising alternating conductive and insulative tiers, where channel-material strings extend through these tiers, and conductively-doped semiconductive material is formed in the lower tier to electrically couple with the channel material, accompanied by undoped semiconductive material in void spaces to optimize electrical conduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional fabrication methods are used to form memory arrays, then manufacturing process is simpler, but undesired etching occurs and electrical coupling precision deteriorates

Engineering Contradiction:

Improveelectrical coupling precisionVSAvoidfabrication process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fabrication process is segmented into distinct stages: forming the conductor tier with initial conducting material, selectively removing portions to create openings, and then forming conductively-doped semiconductive material in specific regions. This segmentation allows precise control over where electrical coupling occurs, improving manufacturing precision while managing process complexity through systematic division of steps.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by creating regions with different material properties: undoped semiconductive material in void spaces provides electrical isolation, while conductively-doped semiconductive material in contact regions provides electrical coupling. This spatial variation in material quality enables precise control of electrical connections without affecting the entire structure uniformly.

Inventive Principle:

Principle #3Local quality

2Reliability

If conductively-doped semiconductive material is formed against channel material, then electrical coupling is enhanced, but undesired etching increases

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidundesired etching

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

Undoped semiconductive material serves as an intermediary substance filling void spaces between conductively-doped regions. This intermediary material prevents etching from propagating into unwanted areas while allowing the conductively-doped material to maintain reliable electrical coupling with the channel material where needed.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies preliminary anti-action by forming undoped semiconductive material in void spaces before finalizing the conductively-doped regions. This preliminary placement of protective material prevents undesired etching from occurring in the first place, rather than attempting to correct etching damage afterward.

Inventive Principle:

Principle #9Preliminary anti-action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach minimizes undesired etching, enhances electrical coupling, and improves the formation of memory cells by ensuring precise and efficient electrical connections within the memory array, thereby enhancing the overall performance and reliability of the memory array.

Implementation Method 1

conductively-doped semiconductive material is formed in the lower tier to electrically couple with the channel material

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

accompanied by undoped semiconductive material in void spaces to optimize electrical conduction

Methodology Applied

Scientific EffectElectrical insulation: Electrical Resistance

Data Source

PatentUS20230062084A1Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells

Publication Date: 2023.03.02 MICRON TECHNOLOGY INC

AI summary

A memory array comprising strings of memory cells comprises conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprising a vertical stack comprises alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. Other embodiments, including method, are disclosed.