Vertically-Oriented Memory Arrays with Metal Silicide Footers
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Solution Overview
Problem
Current memory architectures face challenges in increasing integration levels, reducing device size and complexity, simplifying fabrication processes, and achieving low resistance wiring to improve speed and throughput.
Innovation Solution
The development of memory array architectures with vertically-oriented transistors and digit lines composed of metal-containing materials, which are formed using methods that include the creation of metal silicide footers and semiconductor bridges with insulative gaps, enabling low resistance and reliable connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional memory architectures are used, then fabrication processes are complex and integration levels are limited, but device size reduction and simplification are hindered
Solution Approach 1:
The patent transitions from planar memory architecture to vertically-oriented transistor structures with digit lines extending beneath transistors in the vertical dimension. This dimensional change enables higher integration levels by utilizing the vertical space beneath existing transistor structures for low-resistance digit line connections, thereby increasing functional density without proportionally increasing device footprint.
Solution Approach 2:
The patent implements nested structures where metal-containing digit line materials are formed within and beneath transistor structures. The digit lines are positioned in trenches beneath the transistor channels, with metal silicide footers nested at the bottom of trenches and metal-containing rails extending upward. This nesting approach allows multiple functional elements to occupy overlapping spatial regions, reducing overall device complexity.
2Productivity
If integration levels are increased, then device density improves, but wiring resistance increases
Solution Approach 1:
The patent employs composite metal-containing structures for digit lines, combining multiple materials with complementary properties. Metal silicide footers provide low resistance at critical transistor contact points, while metal-containing rails extending upward provide structural support and continued low-resistance pathways. This composite approach maintains low wiring resistance even as integration levels increase and interconnect lengths grow.
Solution Approach 2:
The patent performs preliminary formation of metal silicide footers and metal-containing digit line structures before completing transistor fabrication. By establishing low-resistance digit line pathways in advance, subsequent processing steps can focus on transistor formation without compromising interconnect quality. This preliminary action ensures that wiring resistance is optimized before integration density becomes the primary constraint.
3Area of stationary object
If device size is reduced, then integration density increases, but fabrication precision requirements increase
Solution Approach 1:
The patent segments the digit line structure into distinct functional components: metal silicide footers at the trench bottom for transistor contact, metal-containing rails extending upward for interconnection, and insulative material filling gaps between structures. This segmentation allows each component to be optimized independently for its specific function, reducing the precision requirements for the overall structure while maintaining high integration density.
Solution Approach 2:
The patent introduces insulative material as an intermediary substance filling gaps between metal-containing digit line structures and transistor components. This intermediary material provides electrical isolation, mechanical support, and stress relief, enabling closer spacing of digit lines and transistors without compromising functionality. The insulative mediator allows device size reduction while maintaining adequate manufacturing precision margins.
Data Source
AI summary
Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.