Memory Array Panel With Offset Bottom Surface
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The configuration of conductive structures in conventional memory devices can lead to misalignment issues, causing shorts and parasitic capacitance between adjacent structures, which complicates the fabrication process and reduces scalability.
Innovation Solution
The proposed solution involves forming memory blocks with intervening panels that have elevationally offset bottom surfaces, separating the memory blocks and conductive structures, and using support structures to maintain electrical connectivity while preventing shorts and capacitance issues. This configuration includes a conductive expanse in the memory array region and an electrically floating or reference-voltage-coupled expanse in the staircase region, with bridging structures at a different elevational level to reduce interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conductive structures are tightly packed to increase memory density, then productivity is improved, but manufacturing precision deteriorates due to misalignment issues causing shorts and parasitic capacitance
Solution Approach 1:
An intervening panel is introduced as a mediator structure between adjacent memory blocks. This panel includes a first portion supported by a first conductive expanse and a second portion supported by a second conductive expanse, with the second portion elevationally offset from the first portion. The intervening panel acts as a buffer that prevents direct contact between adjacent conductive structures, eliminating shorts and parasitic capacitance while allowing tight packing for high density.
2Reliability
If conductive structures are separated to improve manufacturing precision and eliminate shorts, then reliability is improved, but device complexity increases due to additional support structures
Solution Approach 1:
The solution moves the separation mechanism from the planar dimension to the vertical dimension. The second portion of the intervening panel is elevationally offset from the first portion, creating a vertical separation between adjacent memory blocks. This dimensional transition allows electrical isolation without requiring complex lateral spacing or additional planar structures, thereby reducing overall device complexity while maintaining reliability.
3Manufacturing precision
If precise alignment is required to prevent shorts, then manufacturing precision is improved, but ease of manufacture deteriorates due to complicated fabrication processes
Solution Approach 1:
The first portion of the intervening panel is formed to be supported by the first conductive expanse before the second portion is formed to be supported by the second conductive expanse. This preliminary formation establishes a stable reference structure that simplifies subsequent alignment steps. By pre-forming the first portion and using it as a reference, the fabrication process becomes more straightforward while maintaining the precision needed to prevent shorts.
Data Source
AI summary
Some embodiments include an integrated assembly having a memory array region which includes channel material pillars extending through a stack of alternating conductive and insulative levels. A second region is adjacent the memory array region. A conductive expanse is within the memory array region and electrically coupled with the channel material of the channel material pillars. A panel extends across the memory array region and the second region. The panel separates one memory block region from another. The panel has a first portion over the conductive expanse, and has a second portion adjacent the first portion. The panel has a bottom surface. A first segment of the bottom surface is adjacent an upper surface of the conductive expanse. A segment of the bottom surface within the second portion is elevationally offset relative to the first segment. Some embodiments include methods of forming integrated assemblies.