Memory Array Precharge Logic for Power Savings
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Solution Overview
Problem
Prior art domino SRAM designs consume excessive power due to the precharging and discharging of all global bit lines during each cycle, leading to high power dissipation and stability issues in memory arrays.
Innovation Solution
The implementation of identification logic that sends a precharge enable signal only to a subset of precharge logic on each clock cycle, allowing only the necessary global bit lines to be precharged, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all global bit lines are precharged during each cycle in prior art domino SRAM designs, then the memory array is prepared for read operations, but power consumption increases excessively
Solution Approach 1:
The patent divides the global bit lines into multiple groups, with each group associated with a separate precharge logic unit. The identification logic segments the precharge operation by selectively enabling only the precharge logic units corresponding to active bit line groups, rather than precharging all global bit lines uniformly. This segmentation allows the system to maintain read operation readiness for accessed memory regions while avoiding unnecessary precharging of inactive regions, thereby reducing overall power consumption.
2Productivity
If precharge logic is provided for each global bit line, then bit line precharging capability is maximized, but device complexity increases
Solution Approach 1:
The patent implements precharge logic units that can serve multiple global bit lines through selective activation. Each precharge logic unit is designed to handle a group of bit lines rather than being dedicated to a single bit line. The identification logic determines which precharge logic units need to be activated based on the memory access pattern, allowing a smaller number of multi-functional precharge logic units to replace what would otherwise require many single-purpose units, thus reducing device complexity while maintaining full precharging capability.
3Use of energy by moving object
If identification logic selectively enables subset of precharge logic, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The identification logic acts as an intermediary component that bridges the memory access control signals and the precharge logic units. It receives information about which memory cells are being accessed and translates this into selective activation of the corresponding precharge logic units. By positioning the identification logic as an intermediary layer, the patent enables fine-grained control over precharge operations without requiring complex direct control circuitry for each individual bit line, thus achieving power reduction with manageable added complexity.
Data Source
AI summary
A memory array is provided that comprises a plurality of global bit lines such that each bit line is coupled to a plurality of memory cells. The memory array further comprises a plurality of precharge logic such that each precharge logic is coupled to an associated global bit line in the plurality of global bit lines. Identification logic in the memory array is coupled to the plurality of precharge logic. The identification logic provides a precharge enable signal to a subset of the plurality of precharge logic on each clock cycle such that the subset of precharge logic precharges its associated subset of global bit lines to a voltage level of a voltage source, thereby reducing the power consumption of the memory array.