Memory Array Redundancy Removal via Output Merging
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Solution Overview
Problem
Formal verification tools face a bottleneck when dealing with large memory arrays due to bit-blasting, which results in exponential computational resources and incomplete verification coverage, limiting their ability to efficiently identify and remove redundancy and perform equivalence checking in integrated circuit designs.
Innovation Solution
A method for efficient redundancy identification and removal in integrated circuits with memory arrays, involving array merging, equivalence checking, and precluding potentially redundant array cells from participating in sequential redundancy removal, by converting out-of-bounds or disabled array outputs to random outputs and determining enabled array outputs for equivalence testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification tools use bit-blasting to verify large memory arrays, then verification completeness is improved, but computational resources become exponential and verification time increases dramatically
Solution Approach 1:
The patent merges equivalent array outputs into a single representative output. By detecting when multiple array outputs are functionally equivalent (through equivalence checking), the tool consolidates them into one, reducing the total number of signals that need to be bit-blasted and verified, thereby reducing exponential computational resources while maintaining verification completeness
Solution Approach 2:
The patent extracts and removes redundant array outputs from the verification process. By identifying array outputs that are functionally equivalent or redundant, the tool removes them from the bit-blasting process, reducing the verification problem size while maintaining the essential verification coverage through the remaining representative outputs
2Measurement precision
If formal verification tools bit-blast memory arrays into simpler primitives, then verification accuracy is improved, but the size of the verification problem grows exponentially
Solution Approach 1:
The patent combines multiple array outputs into a single representative output through equivalence checking. This merging reduces the number of individual signals that need to be bit-blasted into primitives, thereby reducing the overall verification problem size while maintaining verification accuracy through the representative output that captures the behavior of all equivalent outputs
3Reliability
If the verification process includes all array outputs, then verification coverage is improved, but redundancy removal becomes less efficient
Solution Approach 1:
The patent performs preliminary equivalence checking and redundancy removal before the main verification process. By pre-identifying and removing redundant array outputs, the tool reduces the number of outputs that need to be verified, improving redundancy removal efficiency while maintaining verification coverage through the remaining non-redundant outputs
Solution Approach 2:
The patent merges equivalent array outputs into a single representative output, which improves redundancy removal efficiency by reducing the number of outputs to process. This merging maintains verification coverage because the representative output captures the functional behavior of all equivalent outputs
Data Source
AI summary
A mechanism is provided for efficient redundancy identification, redundancy removal, and sequential equivalence checking with designs including memory arrays. The mechanism includes an array merging component to optimally merge an array output such that if the address is out-of-bounds or the port is not asserted, the array output is converted to a random output. The mechanism also includes a component for determining the equivalence of enabled array outputs rather than the array outputs directly and creating an enabled array output. The mechanism also includes a component that precludes potentially-redundant array cells from participating in the sequential redundancy removal determination. This component first checks for compatibility of the corresponding arrays, then the corresponding read port enables and addresses, then the corresponding initial values, and finally checking that writes to the corresponding columns yield a compatible set of values.