Self-Correcting Memory Array Using Row Comparison for Error Detection
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Solution Overview
Problem
SRAM memory arrays face challenges in detecting and correcting localized data corruption caused by external factors like radiation, which can lead to unpredictable results, and existing error-correcting mechanisms are either inefficient or require additional bits for error detection and correction.
Innovation Solution
A non-destructive memory array with NOR gates and bit lines that perform Boolean operations to compare data across rows, providing a positive change indication when bits differ, allowing for simultaneous error detection and correction without additional bits or complex calculations, using a self-correcting memory device (SCMD) that compares multiple copies of data to identify and correct errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error-correcting code (ECC) is used to detect and correct errors in memory, then data reliability is improved, but additional bits are required for error detection and correction
Solution Approach 1:
The patent merges the data storage function with the error detection function by using the same memory cells to store both data and comparison results. The memory array stores multiple copies of data, and the same array is used to perform comparisons, eliminating the need for separate error detection hardware or additional dedicated bits for error information.
Solution Approach 2:
The memory array is designed to serve multiple functions: storing data, storing multiple copies of data for comparison, and performing error detection through Boolean operations. The bit lines and word lines are used both for data access and for error detection operations, making the memory system universal and multi-functional.
2Reliability
If traditional error detection mechanisms are implemented, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The memory system performs error detection on its own without requiring external error detection hardware or complex control logic. By storing multiple copies of data in the same memory array and using Boolean operations (AND, OR, NOR) to compare them, the system self-detects errors through the natural behavior of the memory cells and bit lines.
Solution Approach 2:
The patent replaces traditional mechanical or electronic error detection hardware with a software-like logical approach using Boolean operations. Instead of using separate comparators or error detection circuits, the system uses logical AND, OR, and NOR operations performed by the memory array itself to detect errors, simplifying the physical hardware required.
3Reliability
If multiple error correction codes are used to ensure data integrity, then data validity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments data into multiple copies stored in different locations within the memory array. Each copy can be independently accessed and compared, allowing error detection without requiring high-precision manufacturing of a single complex error correction system. The segmentation of data into redundant copies simplifies the manufacturing requirements while maintaining data validity.
Data Source
AI summary
A memory device includes a non-destructive memory array that includes memory cells arranged in rows and columns. The array includes a plurality of word lines, first bit lines and second bit lines, a NOR gate per column Each word line activates memory cells in a row and thereby establishes an activated row. First bit lines and second bit lines connect memory cells in columns, each first bit line provides the result of a Boolean AND operation between data stored in the first activated row and data stored in the second activated row. Each second bit line provides the result of a Boolean NOR operation between data stored in the first activated row and data stored in the second activated row. Each per-column NOR gate is connected to the first and second bit lines of each column and compares data stored in the first activated row with data stored in the second activated row.