3D Memory Array Gate-Last Stack for Selective Oxide Etching
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Solution Overview
Problem
Current methods for forming integrated circuitry, particularly memory arrays, face challenges in efficiently creating vertically-stacked memory cells with precise control over conductive and insulative tiers, leading to suboptimal performance and reliability.
Innovation Solution
A 'gate-last' or 'replacement-gate' process is employed, involving the formation of a stack with alternating doped silicon dioxide and undoped silicon dioxide tiers, where doped silicon dioxide is selectively etched relative to undoped silicon dioxide to create void spaces for conducting material, enabling the formation of vertically-extending strings of memory cells with improved electrical isolation and access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form vertically-stacked memory cells, then manufacturing process is simpler, but manufacturing precision and electrical isolation are suboptimal
Solution Approach 1:
The insulative material is segmented into multiple tiers (first insulative tier, second insulative tier, third insulative tier) with different etch selectivities. This segmentation allows selective removal of specific tiers to create precisely positioned void spaces for conductive material, enabling controlled electrical isolation and connection paths in the vertically-stacked memory structure.
Solution Approach 2:
The insulative tiers are formed in advance with predetermined etch selectivities relative to the conductive material. This preliminary configuration of insulative layers with different properties enables subsequent selective etching processes to create the desired void spaces and electrical isolation structures without requiring additional complex processing steps.
2Reliability
If selective etching of doped silicon dioxide is employed, then electrical isolation is improved, but manufacturing complexity increases
Solution Approach 1:
Different regions of the insulative material are given different local qualities through doping. The first insulative tier contains doped silicon dioxide with different etch selectivity compared to the second and third insulative tiers. This local quality variation enables selective etching of specific regions to create void spaces while maintaining electrical isolation in other regions.
Solution Approach 2:
The etch selectivity parameter of the insulative material is changed by doping silicon dioxide in specific tiers. This parameter change creates differential etchability between tiers, allowing the etching process to selectively remove doped silicon dioxide while leaving undoped silicon dioxide intact, thereby creating precisely positioned void spaces for conductive material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the formation of memory arrays by improving electrical isolation and access, leading to more reliable and efficient integrated circuitry with enhanced performance.
Implementation Method 1
Through the trenches, the doped silicon dioxide that is in the first tiers is etched selectively relative to the undoped silicon dioxide that is in the second tiers
Data Source
AI summary
A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise doped silicon dioxide and the second tiers comprise undoped silicon dioxide. Horizontally-elongated trenches are formed into the stack. Through the trenches, the doped silicon dioxide that is in the first tiers is etched selectively relative to the undoped silicon dioxide that is in the second tiers. Conducting material is formed in the void space in the first tiers that is left by the etching. Structure independent of method is disclosed.