Memory Array Shared Gain Transistors for Improved Read SNR
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Solution Overview
Problem
Existing memory technologies, particularly 3D memory devices, suffer from low signal-to-noise ratio (SNR) issues, leading to errors in read values, especially at low temperatures, due to parasitic capacitance loading vertical bitlines.
Innovation Solution
Implementing a memory array with shared gain elements, where control lines are coupled with the gate terminals of transistors instead of directly connecting to sense amplifiers, amplifying the sensed voltage to improve SNR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control lines are directly connected to sense amplifiers, then device complexity is reduced, but signal-to-noise ratio deteriorates due to parasitic capacitance loading
Solution Approach 1:
A gain element transistor is introduced as an intermediary component between the control line and the sense amplifier. The gate of this transistor is connected to the control line, and it acts as a voltage amplifier to boost the signal before it reaches the sense amplifier, thereby improving the signal-to-noise ratio without directly increasing the complexity of the control line connections
Solution Approach 2:
The invention changes the electrical parameters of the control line by using the gain element transistor to amplify the voltage signal. By controlling the gate voltage through the transistor, the signal amplitude is increased, which improves the signal-to-noise ratio and reduces the impact of parasitic capacitance loading
2Reliability
If gain elements are added to amplify signals, then signal-to-noise ratio improves, but device complexity increases
Solution Approach 1:
The gain element transistor serves multiple functions: it acts as a voltage amplifier to boost the signal, provides impedance matching between the control line and sense amplifier, and can be configured to work with multiple memory cells through shared control lines. This multi-functionality justifies the added complexity by delivering multiple benefits from a single component
Solution Approach 2:
Multiple memory cells share common control lines and gain elements, consolidating multiple signal amplification functions into fewer shared components. This merging approach improves the signal-to-noise ratio for all connected memory cells while minimizing the total number of discrete gain elements required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the signal-to-noise ratio, reducing errors in read values and improving memory performance, especially at low temperatures.
Implementation Method 1
a transistor with a gate terminal coupled with the control line and a source terminal and a drain terminal, wherein the sensed voltage on the control line is amplified by the transistor
Data Source
AI summary
Integrated circuit (IC) devices including a memory array and shared gain elements are disclosed herein. In one example, an IC device includes a plurality of memory cells over the substrate, a control line coupled with the plurality of memory cells, and a transistor (e.g., a shared gain/sense transistor) over the substrate and coupled with the plurality of memory cells, where the transistor includes a gate terminal coupled with the control line. In one such example, the shared gain/sense transistor can enable an improved signal-to-noise ratio (SNR).