3D Memory Array Conductor Tiers for Controlled Silicide Contacts
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Solution Overview
Problem
Existing memory array technologies face challenges in efficiently forming vertically-stacked memory cells with reliable electrical connections and minimizing undesired silicide formation during the manufacturing process.
Innovation Solution
The method involves forming a memory array with a 'gate-last' or 'replacement-gate' process, creating a through-array-via (TAV) region using conductive and insulative tiers, and replacing sacrificial materials with conductive materials to establish electrical connections between channel material strings and conductor tiers, while minimizing silicide formation through controlled reactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory array formation processes are used, then manufacturing simplicity is maintained, but undesired silicide formation occurs and electrical connection reliability is compromised
Solution Approach 1:
The patent applies preliminary action by forming the conductor tier with controlled silicide regions before forming the channel material strings. The sacrificial material is pre-positioned to define where silicide should form, and the conductor tier is deposited to create controlled silicide interfaces. This preliminary structuring prevents uncontrolled silicide formation later while ensuring reliable electrical connections at the intended locations.
Solution Approach 2:
The patent uses sacrificial material as an intermediary to control silicide formation. The sacrificial material is temporarily placed to define the exact locations where silicide should form during subsequent processing steps. After the conductor tier is formed with controlled silicide at these locations, the sacrificial material is removed, leaving precisely controlled silicide regions that enable reliable electrical connections without undesired silicide formation elsewhere.
2Productivity
If vertically-stacked memory cells are formed with traditional processes, then three-dimensional integration is achieved, but manufacturing complexity increases and connection reliability decreases
Solution Approach 1:
The patent segments the memory array formation into distinct functional tiers: conductor tiers with controlled silicide regions, insulative tiers, and channel material strings. Each tier is formed and processed separately with specific functions, allowing complex three-dimensional structures to be built through systematic segmentation rather than monolithic processing, thereby reducing overall manufacturing complexity.
Solution Approach 2:
The patent changes material parameters by using different compositions for upper and lower conductor materials in the conductor tier. This parameter change allows optimization of electrical properties at different interfaces and enables controlled silicide formation with specific characteristics. The insulative and conductive materials have carefully selected parameters to enable reliable vertical electrical connections while maintaining manufacturing feasibility.
Data Source
AI summary
A memory array comprising strings of memory cells comprises a conductor tier. The conductor tier comprises upper conductor material directly above and directly against lower conductor material of different composition from that of the upper conductor material. The channel-material strings directly electrically couple to the upper and lower conductor materials of the conductor tier. A through-array-via (TAV) region is included and comprises TAVs. The TAVs individually comprise the upper conductor material, the lower conductor material, and a conducting material that is directly below the conductor tier. The lower conductor material is directly against the upper conductor material and directly against the conducting material. The lower conductor material comprises a metal-rich refractory metal nitride directly above and directly against a non-metal-rich refractory metal nitride that is directly against the conducting material. The lower conductor material may also comprise a first elemental-form metal directly above and directly against a second elemental-form metal that is directly against the conducting material Methods are also disclosed.