3D Memory Array Stack Layout for Conductive Seam and Isolation Control
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Solution Overview
Problem
Current methods for forming memory arrays, such as NAND architecture, face challenges in efficiently integrating vertically-stacked memory cells with effective gate structures and peripheral control circuitry, particularly in maintaining precise material compositions and etching processes to ensure reliable electrical connectivity and isolation between memory blocks.
Innovation Solution
The method involves forming a stack with alternating conductive and insulative tiers, using sacrificial materials like carbon and nitrogen-containing compounds, and employing isotropic etching to create channel-material strings and trenches, followed by the formation of conductive lines and charge-blocking regions, allowing for the precise construction of memory cells and control circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If vertically-stacked memory cells are integrated with peripheral control circuitry, then memory array functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The memory array is divided into multiple memory blocks (first memory block, second memory block, etc.) with distinct wordline tiers and bitline connections. Each memory block can be independently controlled through separate control gates, allowing selective operation of specific memory regions while simplifying the overall manufacturing process by modularizing the complex integration of memory cells and control circuitry.
Solution Approach 2:
The patent transitions from planar memory architecture to three-dimensional vertically-stacked memory cells arranged in multiple tiers. Memory cells are stacked vertically with control gates positioned at different elevation levels (first control gate tier, second control gate tier), enabling higher density integration while maintaining manufacturability through standardized vertical fabrication processes.
2Reliability
If precise material compositions and etching processes are maintained, then electrical connectivity and isolation reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
Sacrificial materials (such as silicon nitride or other etch-stop layers) are introduced as intermediary layers between the memory cell structures and control gates. These sacrificial materials facilitate precise etching processes by providing clear etch-stop planes, ensuring reliable electrical isolation between adjacent memory blocks and control circuitry while maintaining consistent material compositions throughout the fabrication process.
Solution Approach 2:
The patent employs controlled etching parameters and material composition variations at different vertical levels. By adjusting etch selectivity, depth, and chemistry based on the specific layer being processed, the method achieves reliable electrical connectivity within memory blocks and isolation between blocks without requiring uniformly extreme precision across all manufacturing steps.
3Strength
If conductive material seams are prevented, then structural integrity of memory cells is improved, but manufacturing process complexity increases
Solution Approach 1:
Conductive material layers are continuously formed across the entire substrate area before any etching or patterning steps that would create discontinuities. The conductive layers (such as bitlines, wordlines, or control gates) are deposited as uniform continuous films that span across multiple memory blocks, ensuring inherent structural integrity and preventing seam formation. Subsequent processing steps selectively remove or pattern these pre-formed continuous conductive layers rather than attempting to join separate segments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of reliable memory arrays with improved electrical connectivity and isolation, reducing the tendency for seams in conductive material and enhancing the overall structural integrity and performance of the memory cells.
Implementation Method 1
The sacrificial material is isotropically etched from the lowest first tier through the trenches
Data Source
AI summary
Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks that individually comprise a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises alternating first insulating tiers and second insulating tiers. The lower portion comprises a lowest insulator tier directly above conductor material of a conductor tier. The lowest insulator tier comprises solid carbon and nitrogen-containing material. An immediately-adjacent tier is directly above the solid carbon and nitrogen-containing material of the lowest insulator tier. The immediately-adjacent tier comprises material that is of different composition from that of the lowest insulator tier. Other embodiments, including methods, are disclosed.