Memory Array Multiplexing for Row and Transposed Column Access
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Solution Overview
Problem
Existing memory devices for AI applications require extra buffers and macros for data rearrangement, leading to increased power consumption, latency, and device size due to inefficient row-wise and column-wise data access.
Innovation Solution
A memory device with integrated multiplexers that allow for both row-wise and transposed column-wise data access, eliminating the need for additional buffers and macros, thereby optimizing power, latency, and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If extra buffers and macros are added for data rearrangement, then data access flexibility is improved, but device size increases
Solution Approach 1:
The memory device integrates both row-wise and column-wise access capabilities into a single memory array structure, allowing the same hardware to perform multiple access patterns without requiring separate buffers or macros for each access type
Solution Approach 2:
The patent combines row-wise and column-wise access paths within the same memory device, merging previously separate functionality into a unified structure that eliminates the need for additional dedicated hardware components
2Adaptability or versatility
If extra buffers and macros are added for data rearrangement, then data access flexibility is improved, but power consumption increases
Solution Approach 1:
The memory device provides multiple access patterns through a single unified structure, eliminating the need for additional buffers and macros that would consume extra power, thereby achieving energy-efficient multi-functional operation
Solution Approach 2:
The patent extracts and eliminates the unnecessary extra buffers and macros from the traditional memory architecture, retaining only the essential memory array with integrated access paths, thereby reducing power consumption while maintaining access flexibility
3Adaptability or versatility
If extra buffers and macros are added for data rearrangement, then data access flexibility is improved, but latency increases
Solution Approach 1:
By merging row-wise and column-wise access paths within the same memory device and eliminating intermediate buffers and macros, the patent reduces the number of processing stages and data transfer steps, thereby reducing latency while maintaining access flexibility
4Device complexity
If traditional row-wise access is used, then hardware simplicity is maintained, but data rearrangement efficiency deteriorates
Solution Approach 1:
The memory device provides both row-wise and column-wise access capabilities through a single unified structure, enabling efficient data rearrangement for AI workloads while maintaining hardware simplicity by avoiding additional dedicated hardware components
Data Source
AI summary
A device including a memory array configured to store data in memory cells, read circuits configured to read the data out of the memory cells, and a plurality of input/output (I/O) terminals. A first plurality of multiplexers is configured to retrieve the data out of the memory cells and transmit the data to the plurality of I/O terminals in a first sequence of rows of data, and a second plurality of multiplexers is configured to retrieve the data out of the memory cells and transmit the data to the plurality of I/O terminals in a second sequence of columns of data that are transposed from the first sequence of rows of data.