Memory Bandwidth Control via Credit Counters

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Solution Overview

Problem

In microprocessor systems, managing cache prefetching and memory accesses efficiently across multiple clients in a processor cluster is challenging due to varying memory bandwidth usage, leading to potential bottlenecks and inefficiencies in resource allocation.

Innovation Solution

The system partitions resources into client-specific portions, tracks memory bandwidth usage states, and adjusts a credit count to determine when to issue data access requests, ensuring that requests are managed based on individual client usage levels to optimize memory access efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory bandwidth is shared among multiple clients in a processor cluster, then resource utilization improves, but memory access efficiency deteriorates due to bandwidth contention and varying usage patterns

Engineering Contradiction:
Improveresource utilizationVSAvoidmemory access efficiency
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The patent segments memory bandwidth resources by implementing separate credit counters and usage trackers for each client (tenant). Each client receives dedicated memory access credits independent of others, allowing simultaneous memory operations without contention. This segmentation resolves the contradiction by enabling multiple clients to access memory efficiently in parallel while maintaining individual resource guarantees.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic credit allocation and adjustment mechanisms where memory access credits are allocated based on client usage patterns, priorities, and current system state. The credit counters are dynamically updated as clients consume memory bandwidth, enabling adaptive resource management that optimizes both utilization and access efficiency under varying workloads.

Inventive Principle:
Principle #15Dynamics

2Speed

If cache prefetching is enabled to improve data availability, then processing speed improves, but memory bandwidth consumption increases causing bottlenecks

Engineering Contradiction:
Improveprocessing speedVSAvoidmemory bandwidth consumption
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent implements partial prefetching controlled by credit availability rather than aggressive full prefetching. Prefetch operations are issued proportionally to available memory credits, allowing the system to perform beneficial prefetching to improve processing speed while constraining total memory bandwidth consumption through credit-based rate limiting.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent employs feedback mechanisms where memory access patterns, credit consumption rates, and bandwidth utilization are continuously monitored. This feedback informs dynamic adjustment of prefetching intensity and credit allocation, enabling the system to optimize the balance between processing speed improvements from prefetching and memory bandwidth conservation.

Inventive Principle:
Principle #23Feedback

3Ease of operation

If memory access requests are issued without control to satisfy client demands, then client service quality improves, but system bottlenecks increase due to unmanaged bandwidth usage

Engineering Contradiction:
Improveclient service qualityVSAvoidsystem bottlenecks
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent allocates memory access credits to clients in advance based on their resource portions and usage patterns. This preliminary credit allocation enables clients to immediately issue memory access requests without real-time negotiation or arbitration, improving service quality and responsiveness while the credit system pre-established boundaries prevent system bottlenecks.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11899964B2Methods and systems for memory bandwidth control
Publication Date: 2024.02.13 QUALCOMM INC
  • US11899964B2 patent drawing
  • US11899964B2 patent drawing
  • US11899964B2 patent drawing

AI summary

Resources of an electronic device are partitioned into a plurality of resource portions to be utilized by a plurality of clients. Each resource portion is assigned to a respective client, has a respective partition identifier (ID), and corresponds to a plurality memory bandwidth usage states tracked for a plurality of memory blocks. For each resource portion, each of the memory bandwidth usage states is associated with a respective memory block and indicates at least how much of a memory access bandwidth assigned to the respective partition ID to access the respective memory block is used. A usage level is determined for each resource partition based on the memory bandwidth usage states, and applied to adjust a credit count. When the credit count is adjusted beyond a request issue threshold, a next data access request is issued from a memory access request queue for the respective partition ID.