Process Scheduling via Memory Bandwidth Quotas

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current process schedulers face challenges in efficiently managing shared hardware resources, leading to performance bottlenecks and instability in I/O-bound applications, particularly in multi-core systems, where CPU quota alone is insufficient to guarantee performance and Quality of Service (QoS), often requiring costly overprovisioning or shutting down cores.

Innovation Solution

Implementing a method that controls process execution based on a usage bound of allowable accesses to shared hardware resources, halting execution when the limit is reached and enabling idle mode or starting the next process, thereby avoiding costly overprovisioning and core shutdowns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If CPU time division is used as the main scheduling mechanism, then CPU-bound applications are adequately supported, but I/O-bound applications experience memory congestion and performance bottlenecks

Engineering Contradiction:
ImproveCPU utilization efficiencyVSAvoidI/O-bound application performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the scheduling parameter from CPU time quota to memory bandwidth quota. Instead of allocating CPU time in traditional scheduling, the system allocates memory bandwidth to processes, fundamentally changing how resource allocation works to address I/O-bound application needs.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces memory bandwidth as an intermediary resource for scheduling. Rather than directly scheduling based on CPU time, the system uses memory bandwidth allocation as a mediator to control process execution, which indirectly manages CPU utilization while ensuring I/O-bound applications receive adequate memory access resources.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If hardware resources are overprovisioned to guarantee stable execution, then QoS is ensured, but system cost increases significantly

Engineering Contradiction:
ImproveQoS guaranteeVSAvoidhardware resource allocation
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies preliminary action by pre-allocating memory bandwidth quotas to processes before execution begins. This allows the system to guarantee QoS through planned resource distribution rather than requiring excessive hardware overprovisioning, as the bandwidth allocation is established in advance and enforced during execution.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

By changing the scheduling parameter from CPU time to memory bandwidth, the system achieves QoS guarantees without needing to overprovision hardware. The bandwidth quota mechanism provides a more efficient way to ensure service level agreements, reducing the quantity of hardware resources needed while maintaining reliability.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If adjacent cores are shut down to avoid shared resource interference, then I/O-bound application performance is protected, but hardware resource utilization decreases

Engineering Contradiction:
Improveapplication execution stabilityVSAvoidhardware resource utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by assigning different memory bandwidth quotas to different processes based on their specific needs and interference characteristics. Instead of uniformly shutting down adjacent cores, the system provides tailored bandwidth allocations that allow co-location of I/O-bound applications while managing shared resource interference through differentiated resource distribution.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system dynamically adjusts process execution based on real-time memory bandwidth consumption and shared resource usage patterns. Rather than static core shutdowns, the scheduler dynamically manages process placement and execution to optimize both stability and resource utilization, allowing flexible adaptation to changing workload conditions.

Inventive Principle:
Principle #15Dynamics

4Device complexity

If CPU quota alone is used for scheduling in multi-core systems, then implementation is simple, but performance guarantees cannot be provided due to shared resource interference

Engineering Contradiction:
Improvescheduling mechanismVSAvoidperformance guarantee
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces memory bandwidth as an intermediary scheduling parameter that mediates between CPU allocation and actual application performance. This intermediary resource provides a more direct link to I/O-bound application needs, enabling performance guarantees while maintaining relatively simple scheduling implementation through bandwidth quota enforcement.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11216301B2Process scheduling in a processing system having at least one processor and shared hardware resources
Publication Date: 2022.01.04 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US11216301B2 patent drawing
  • US11216301B2 patent drawing
  • US11216301B2 patent drawing

AI summary

A method for enabling scheduling of processes in a processing system having at least one processor and associated hardware resources, at least one of the hardware resources being shared by at least two of the processes. The method is characterized by controlling execution of a process based on a usage bound of the number of allowable accesses, by the process, to a shared hardware resource by halting execution of the process when the number of allowable accesses has been reached, and enabling idle mode or start of execution of a next process. In this way, costly hardware overprovisioning and/or the need for shutting down processor cores can be avoided. By controlling execution of a process based on a usage bound of the number of allowable accesses to a shared hardware resource, instead of simply dividing CPU time between processes, highly efficient shared-resource-based process scheduling can be achieved.