Configurable Memory Bank Modes for In-Memory Processing Balance
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Solution Overview
Problem
Semiconductor memory devices face challenges in efficiently balancing arithmetic processing and normal memory operations, leading to decreased memory operation speed due to resource allocation demands for vast computations.
Innovation Solution
A memory device with configurable mode setting, allowing adaptive adjustment of bank regions to operation or memory modes based on computation demands, using processing elements and control logic to optimize resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processing elements are integrated into the memory device to perform arithmetic processing, then computation capability is improved, but memory operation speed deteriorates due to resource allocation demands
Solution Approach 1:
The memory device is divided into multiple bank regions, with each bank region independently controllable for operation mode or memory mode. This segmentation allows simultaneous execution of arithmetic processing in some banks while maintaining high-speed memory operations in others, thus resolving the contradiction between computation capability and memory operation speed.
Solution Approach 2:
The memory device dynamically adjusts the operational state of different bank regions based on computation demands. When arithmetic processing is required, specific banks are configured as operation mode; when memory performance is prioritized, banks are set to memory mode. This dynamic configuration enables the system to adaptively balance computation capability and memory operation speed.
2Power
If resources are allocated for vast arithmetic processing, then computation performance is improved, but normal memory operation speed decreases
Solution Approach 1:
Different bank regions are assigned different functional qualities based on local needs. Some banks are configured with processing elements for high-performance arithmetic operations, while other banks maintain standard memory architecture for high-speed data access. This local differentiation allows the system to achieve high computation performance in specific regions without compromising overall memory operation speed.
Data Source
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AI summary
A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.