Memory Bank Power Control for Stacked Semiconductor Capacity
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Solution Overview
Problem
High-capacity memory devices with stacked chip packaging structures face challenges with high current and power consumption, leading to increased heating and reduced operational capacity.
Innovation Solution
A semiconductor memory device with a power control circuit that applies specific power voltages or ground voltages to power terminals based on identifiers assigned to memory cells, optimizing power usage and reducing current consumption in non-used circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a plurality of memory chips are stacked to form a multi-chip package memory to increase capacity, then the integration degree and capacity are improved, but the current consumption, power consumption, and heating value increase
Solution Approach 1:
The memory device is divided into multiple independently controllable banks, where each bank can be activated or deactivated based on access requirements. This segmentation allows the system to power down unused banks, reducing overall power consumption while maintaining high capacity through the stacked multi-chip structure.
Solution Approach 2:
The patent implements dynamic power control by selectively enabling or disabling power supply to different banks based on their usage status. This dynamic adjustment of power states allows the system to optimize between capacity utilization and power consumption in real-time, preventing unnecessary power drain in inactive memory regions.
2Quantity of substance
If a plurality of memory chips are stacked to form a multi-chip package memory to increase capacity, then the integration degree and capacity are improved, but the heating value increases
Solution Approach 1:
By segmenting the memory into multiple banks with independent power control, the system can isolate heat generation to only the actively used portions. This spatial segmentation of power consumption reduces overall thermal load and prevents heat accumulation across the entire stacked structure.
Solution Approach 2:
The patent converts the potential harm of high power consumption into a controllable feature by implementing selective banking. The power that would otherwise be wasted in inactive regions is now dynamically managed, turning the heating issue into an opportunity for thermal optimization through selective activation of memory banks based on access patterns.
3Use of energy by moving object
If power control is applied to reduce current consumption in non-used circuits, then power usage is optimized, but circuit complexity increases
Solution Approach 1:
The power control circuit is designed with multi-functionality, serving both as a power management mechanism and as a bank selection control system. This universal circuit performs dual roles: it manages power distribution to reduce consumption while simultaneously controlling which memory banks are accessible, thereby reducing complexity compared to having separate control mechanisms.
Data Source
AI summary
A semiconductor memory device may include a plurality of memory cells wherein identifiers may be provided to the memory cells. The semiconductor memory device may include a first circuit, a second circuit and a power control circuit. The first circuit may include a first power terminal and a second power terminal. The second circuit may include a third terminal and a fourth terminal. The power control circuit may be configured to apply a first power voltage or a ground voltage to the first power terminal and to apply the ground voltage to the second power terminal based on the identifiers.