Semiconductor Memory Bank Precharge Staggering
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Solution Overview
Problem
Conventional semiconductor memory devices experience high power consumption and noise in the power supply voltage during all-bank precharge operations due to simultaneous precharging of multiple banks, which can lead to extended precharge durations and preclude normal operations.
Innovation Solution
A precharge method that controls the start times of individual banks differently during all-bank precharge operations by determining a precharge order based on the active and write orders, activating final precharge signals at varying times to stagger the precharging of banks, and optionally precharging blocks in units to minimize simultaneous power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If all banks are precharged simultaneously during an all-bank precharge operation, then the precharge operation can be completed quickly, but power consumption increases significantly causing noise in the power supply voltage
Solution Approach 1:
The patent segments the simultaneous precharge operation into sequential phases by dividing banks into groups. The precharge controller activates precharge signals for different groups of banks at different times based on latched active orders, thereby distributing the power consumption over time and reducing peak power demands while maintaining operational efficiency
2Productivity
If all banks are precharged simultaneously, then the precharge operation is completed in minimal time, but noise in the power supply voltage increases
Solution Approach 1:
The patent segments the precharge operation into multiple phases by dividing banks into groups that are precharged sequentially rather than simultaneously. The precharge controller uses latched active orders to determine the sequence, activating precharge signals for different groups at different times, thereby reducing power supply noise while maintaining overall productivity
3Object-generated harmful factors
If banks are precharged sequentially to reduce power consumption, then power noise is reduced, but the precharge operation duration increases
Solution Approach 1:
The patent applies preliminary action by latching the active orders of banks before executing the precharge operation. This pre-captured information enables the precharge controller to optimize the sequential precharge sequence, ensuring that banks are precharged in an order that minimizes both power noise and overall operation duration by anticipating which banks need precharging based on their active states
4Ease of manufacture
If a conventional all-bank precharge command is executed with a fixed delay, then the operation is simple to implement, but it cannot adapt to different bank states leading to inefficiency
Solution Approach 1:
The patent transforms the static, fixed-delay precharge command into a dynamic operation by introducing a precharge controller that latches active orders and dynamically determines the precharge sequence based on current bank states. This dynamic approach maintains implementation simplicity while significantly improving productivity by adapting the precharge operation to the actual states of the banks
Data Source
AI summary
A precharge method of a semiconductor memory device that controls a precharge start time of each bank during a bank precharge operation, and a semiconductor memory device using the method, are provided. The device may latch an active or write order of respective banks and differently control precharge start times of the respective banks according to the latched active or write order during a plural-bank precharge operation to allow a plurality of banks to start precharge operations at different times.