Memory Bank Processing Circuitry for Data Movement Efficiency

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Solution Overview

Problem

Existing processor-in-memory (PIM) devices face challenges in efficiently moving data between and within banks, leading to inefficiencies in data processing time and increased power consumption.

Innovation Solution

The implementation of a memory device with sensing circuitry and compute circuitry formed on pitch with the memory cells, utilizing a shared I/O line for improved data movement, allowing data to be processed and stored locally within the memory array without external processing resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is moved between banks using external processing resources and traditional bus interfaces, then data processing can be performed, but data movement time and power consumption increase

Engineering Contradiction:
Improvedata processing speedVSAvoiddata movement time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent merges the processing resources with the memory banks by implementing processing circuitry directly within each memory bank. This integration allows data to be processed in-place without being transferred to external processing units, thereby eliminating data movement time and improving overall productivity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a bank interface circuit that acts as an intermediary between memory banks and external processing resources. This interface enables direct data exchange between banks while reducing the need for external bus transactions, thus decreasing data movement time and improving processing speed.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If data is moved between banks using external processing resources, then data can be processed, but power consumption increases

Engineering Contradiction:
Improvedata processing capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

By combining processing circuitry with memory banks in an integrated manner, the patent enables data processing to occur locally within each bank. This eliminates the need for data to be transferred to external processing units, thereby reducing power consumption associated with data movement while maintaining full processing capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements self-service processing within each memory bank, where data is processed in-place using locally integrated processing resources. This eliminates the need for external processing interventions and reduces power consumption by avoiding repeated data transfers between memory and external processors.

Inventive Principle:
Principle #25Self-service

3Device complexity

If processing resources are implemented external to the memory array, then device complexity is reduced, but data movement efficiency decreases

Engineering Contradiction:
Improvedevice architectureVSAvoiddata movement efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent merges processing resources with memory banks by integrating processing circuitry directly within each bank. This integration improves data movement efficiency by enabling in-place processing, while the modular bank structure maintains manageable device complexity through standardized interfaces and organized architecture.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3268965B1Apparatuses and methods for data movement
Publication Date: 2025.04.30 LODESTAR LICENSING GROUP LLC
  • EP3268965B1 patent drawingFigure 1A
  • EP3268965B1 patent drawingFigure 1B
  • EP3268965B1 patent drawingFigure 1C

AI summary

The present disclosure includes apparatuses and methods for data movement. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes a sense amplifier and a compute component coupled to a sense line and configured to implement operations. A controller in the memory device is configured to couple to the array and sensing circuitry. A shared I/O line in the memory device is configured to couple a source location and a destination location.