Memory Base Dies With Die-to-Die Links for Scalable Compute
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Solution Overview
Problem
Performance of applications and operations is limited by varying demands on compute and memory resources, necessitating a unified approach to enhance both resources for improved efficiency.
Innovation Solution
Incorporating processing circuits within base dies of memory devices and connecting them to additional memory devices through die-to-die interfaces, along with network devices for expanded compute and memory resources, forming a system-in-package and compute/memory tray architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processing circuits are integrated into base dies and connected through die-to-die interfaces, then compute and memory resources are enhanced, but device complexity increases
Solution Approach 1:
The system is divided into multiple base dies, each containing processing circuits and memory devices. Each base die can be independently manufactured and tested, reducing the complexity of the overall system. The die-to-die interfaces enable modular connectivity, allowing compute and memory resources to be enhanced by adding more base dies without redesigning the entire system.
Solution Approach 2:
Memory devices are attached to base dies, forming a nested structure where memory is integrated within the base die package. This nesting allows memory resources to be closely coupled with processing circuits, enhancing compute and memory resources while maintaining a compact form factor that manages device complexity.
2Quantity of substance
If multiple memory devices are connected through die-to-die interfaces, then memory resources are enhanced, but area occupied increases
Solution Approach 1:
Instead of expanding memory resources in a single plane which would increase area, the patent connects multiple base dies in three-dimensional space through die-to-die interfaces. This vertical stacking approach allows memory resources to be enhanced while minimizing the footprint area occupied by the system.
Data Source
AI summary
Memory devices with processing circuits are disclosed. An apparatus may include a first memory device and a second memory device. The first memory device may include a first base die and a first memory die attached to the first base die. The first base die may include a first processing circuit, a second processing circuit, and a first die-to-die interface. The second memory device may include a second base die and a second memory die attached to the second base die. The second base die may include a third processing circuit and a second die-to-die interface. The first memory device may be configured to communicate with the second memory device using the first die-to-die interface and the second die-to-die interface.