Memory Bias Circuit Segmentation for Faster Power-Down Recovery

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Solution Overview

Problem

In semiconductor memory circuits, the recovery time of the bias circuit is longer than that of the functional circuit, leading to increased tXP time and power consumption when transitioning from a Power Down State to a Power On State.

Innovation Solution

A control circuit with a bias circuit that includes a first bias circuit providing a smaller bias current and a second bias circuit providing a larger bias current, where the first bias circuit is in a normally open state and the second bias circuit is enabled by a bias enabling signal, allowing for controlled power management and reduced recovery time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the bias circuit is powered down to save power, then power consumption is reduced, but the recovery time increases and occupies tXP time

Engineering Contradiction:
Improvepower consumptionVSAvoidrecovery time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The bias circuit is divided into two independent sub-circuits: a first bias circuit that remains powered on continuously, and a second bias circuit that is powered down during Power Down State. This segmentation allows the patent to selectively power only the necessary portion of the bias circuit, reducing overall power consumption while maintaining essential bias current supply through the first bias circuit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first bias circuit is designed to remain powered on in advance before the Power Down State transition, maintaining a ready state that can quickly supplement bias current when needed. This preliminary action ensures that when exiting Power Down State, the first bias circuit is already operational and can immediately provide bias current, reducing the overall recovery time without requiring the entire bias circuit to be fully powered up.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If the bias circuit recovery time is reduced, then tXP time is improved, but power consumption increases

Engineering Contradiction:
ImprovetXP timeVSAvoidpower consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

By segmenting the bias circuit into two parts with different power management strategies, the patent achieves fast recovery (improving tXP time) through the always-on first bias circuit while maintaining power savings through the powered-down second bias circuit during idle states. The combined effect provides both speed and energy efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the bias circuit are assigned different operational characteristics: the first bias circuit operates continuously with higher power consumption but faster response, while the second bias circuit operates intermittently with lower power consumption but slower response. This local differentiation of quality allows the system to optimize both tXP time and power consumption simultaneously by using each portion where it is most effective.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12224741B2Control circuit with bias circuitry for a semiconductor memory
Publication Date: 2025.02.11 CHANGXIN MEMORY TECH INC
  • US12224741B2 patent drawing
  • US12224741B2 patent drawing
  • US12224741B2 patent drawing

AI summary

A control circuit includes a bias circuit. The bias circuit is configured to provide a bias current for a functional circuit. The bias circuit includes a first bias circuit and a second bias circuit. The first bias circuit is configured to provide a first bias current, and the second bias circuit is configured to provide a second bias current. Herein, the first bias current is smaller than the second bias current, the first bias circuit is configured to be in a normally open state after being powered on, and the second bias circuit is configured to receive a bias enabling signal and provide the second bias current based on the bias enabling signal.