Memory Bit Addressing for Byte-Level Error Correction
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Solution Overview
Problem
Existing error correction codes (ECC) for memory devices require sector erase operations, which are time-consuming and detrimental to the device's lifespan, and lack flexibility in byte-level programming.
Innovation Solution
Implementing additional bits in the memory device to identify the address of failing bits, allowing for byte-level programming and correction without sector erase operations, using simpler hardware logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC codes are used to correct bit errors, then error correction capability is improved, but sector erase operations are required which increase time consumption and device wear
Solution Approach 1:
The invention segments the error correction approach by dividing the 64-bit word into individual bit positions and using 6 additional bits to identify which specific bit position contains an error. This allows correction of individual bits without requiring sector-level operations, thus reducing time consumption while maintaining error correction capability.
Solution Approach 2:
The invention adds a new dimension to the storage structure by incorporating 6 additional bits alongside the 64 data bits. These additional bits provide positional information about erroneous bits, enabling targeted correction at the bit level rather than requiring broader sector operations, thereby reducing both time and wear.
2Reliability
If ECC codes are used to correct bit errors, then error correction capability is improved, but device wear increases due to sector erase operations
Solution Approach 1:
By segmenting the correction mechanism to operate at the individual bit level using 6 address bits, the invention eliminates the need for sector erase operations. This segmentation allows precise targeting of only the erroneous bit, significantly reducing wear on the memory device while preserving error correction functionality.
Solution Approach 2:
The invention changes the operational parameter from sector-level erases to bit-level corrections. By using 6 additional bits to encode the position of erroneous bits, the system can correct errors through targeted programming operations rather than broad sector erases, thereby extending device lifespan.
3Reliability
If ECC codes are used to correct bit errors, then error correction capability is improved, but byte-level programming flexibility is lost
Solution Approach 1:
The invention segments the error identification to the individual bit level using 6 address bits, which provides finer granularity than byte-level correction. This bit-level segmentation enables flexible programming at any granularity (byte, word, or individual bit) while maintaining error correction capability, thus improving adaptability rather than reducing it.
Solution Approach 2:
By adding the dimension of bit-position encoding with 6 additional bits, the system gains enhanced flexibility. These additional bits provide precise positional information that enables adaptive correction at multiple levels (individual bits, bytes, or words), thereby improving rather than reducing programming flexibility.
4Measurement precision
If 6 additional bits are used to identify erroneous bit positions, then correction precision is improved, but device complexity increases
Solution Approach 1:
The invention replaces complex ECC decoding hardware with a simpler mechanism that uses 6 additional bits to directly encode bit positions. Instead of requiring complex mathematical decoding operations, the system uses straightforward binary encoding of positions (0-63), significantly reducing hardware complexity while maintaining high precision in error identification.
Data Source
AI summary
Systems and methods to address and correct individual bits within a data word in memory are disclosed. A data word may correspond to a set of additional bits. Logic in a memory controller may be configured to write a code into the additional bits in the event that a bit within the data word is slow to erase or slow to program. A subsequent read operation may then read the data word as well as the additional bits and correct the particular bit in accordance with the code stored to the additional bits.