Semiconductor Memory Bit Line Coupling for Parasitic Capacitance Reduction
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Solution Overview
Problem
The increasing length of bit lines in semiconductor memory devices leads to increased parasitic capacitance and interference between adjacent bit lines, resulting in reduced operating speed due to slower precharging times.
Innovation Solution
The semiconductor memory device incorporates multiple memory block groups coupled to bit lines, with a page buffer group and bit line coupling circuits that selectively couple bit lines to control voltages and reduce parasitic capacitance by optimizing bit line connections and control signals during program and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to increase data storage capacity, then the storage capacity is improved, but the bit line length increases and parasitic capacitance increases, resulting in slower operating speed
Solution Approach 1:
The memory cell array is divided into multiple memory block groups (first, second, third, fourth memory block groups), each coupled to the same bit lines. This segmentation allows the bit lines to serve multiple memory blocks, reducing the overall bit line length required to access the same number of memory cells, thereby reducing parasitic capacitance while maintaining storage capacity.
2Quantity of substance
If the bit line length is increased to access more memory cells, then the storage capacity is improved, but the precharging speed becomes slow, resulting in reduced operating speed
Solution Approach 1:
The memory system is segmented into multiple memory block groups that share common bit lines through bit line coupling circuits. This segmentation reduces the effective bit line length from extending across all memory blocks to serving only four memory block groups, significantly reducing RC time constants and precharging time while maintaining the ability to access the same total number of memory cells.
3Quantity of substance
If the interval between adjacent bit lines is narrowed to increase memory density, then the storage capacity is improved, but parasitic capacitance between adjacent bit lines increases, causing interference and reducing operating speed
Solution Approach 1:
By segmenting the memory into multiple block groups that share bit lines, the patent reduces the total number of bit lines required. This reduction in bit line count increases the spacing between remaining bit lines, thereby reducing parasitic capacitance and interference while maintaining high memory density through efficient sharing of bit line resources across multiple memory blocks.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including memory block groups each coupled to bit lines, a page buffer group coupled to first bit lines of a first memory block group and configured to control voltages of the first bit lines of the first memory block group depending on data to be stored in memory cells in a program operation and configured to sense the voltage of the first bit lines in a read operation, at least one bit line coupling circuit configured to couple first bit lines of a nth memory block group to the page buffer group by selectively coupling first bit lines of the first to nth memory block groups in response to bit line coupling signals, and bit line control circuits configured to control second bit lines of the memory block groups in response to bit line control signals.