Semiconductor Memory Bit Line Programming Order Alternation
Solution Overview
Problem
In semiconductor memory devices, particularly NAND flash memory, the increasing parasitic capacitance between neighboring bit lines leads to interference effects that broaden the threshold distribution, reducing the read margin and complicating data programming as the feature size decreases, especially when data programming is executed in a fixed order between even and odd bit lines.
Innovation Solution
A control circuit is implemented to alternate the order of data programming between even and odd bit lines, ensuring that data programming is executed in both bit lines in a cyclical manner to reduce the effect of capacitive coupling, thereby maintaining a balanced threshold distribution and preventing the broadening of the read margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If data program is executed separately in even-BL and odd-BL to reduce interference effect, then interference between neighboring cells is reduced, but threshold distribution broadens and read margin decreases
Solution Approach 1:
The patent applies periodic action by alternating the execution order of data program between even-BL and odd-BL in a cyclic manner. Instead of executing all even-BL programs followed by all odd-BL programs (fixed order), the system periodically switches between even-BL and odd-BL execution (e.g., even-BL0, odd-BL0, even-BL1, odd-BL1, ...). This periodic alternation prevents continuous capacitive coupling interference from one bit line group to another, thereby maintaining a balanced threshold distribution while still reducing interference effects between neighboring cells.
2Device complexity
If fixed order of data program is used between even and odd bit lines, then control is simplified, but capacitive coupling effect increases and threshold distribution becomes unbalanced
Solution Approach 1:
The patent applies dynamics by making the data program execution order flexible and adaptive rather than fixed. The control circuit dynamically adjusts the execution sequence based on bit line grouping, alternating between even-BL and odd-BL in a structured cyclic pattern. This dynamic approach balances the capacitive coupling effects on both even and odd bit lines, preventing threshold distribution imbalance while maintaining reasonable control complexity through systematic alternation.
3Productivity
If data program is executed in all bit lines simultaneously, then productivity is improved, but interference effect between neighboring cells increases significantly
Solution Approach 1:
The patent applies segmentation by dividing the bit lines into separate groups (even-BL and odd-BL) and executing data program in these groups alternately rather than simultaneously. This segmentation prevents the strong capacitive coupling interference that would occur if all neighboring bit lines were programmed at the same time. The systematic alternation between even-BL and odd-BL groups maintains reasonable productivity by keeping the pipeline full while avoiding the harmful interference of simultaneous programming.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the influence of capacitive coupling, maintains a balanced threshold distribution between even and odd bit lines, improves data programming reliability, and reduces manufacturing costs by eliminating the need for additional parameters and registers.
Implementation Method 1
the increasing parasitic capacitance has been increasing between neighboring BLs and between neighboring cells, leading to a greater interference effect between cells
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory cell array, a column decoder, and a control circuit configured to control the memory cell array and the column decoder. The control circuit is configured to load program data from outside, to execute a first data program in a first even-numbered bit line, to execute a second data program in a first odd-numbered bit line, to execute a verify read of the programmed bit lines, to determine whether a value of the verify read is programmed up to a predetermined threshold value, and to change, in a case where the value of the verify read fails to be programmed to the predetermined threshold value, an order of the first and second data programs, to execute the second data program in the first odd-numbered bit line, and then to execute the first data program in the first even-numbered bit line.