Semiconductor Memory Bit Line Voltage Control for Fast Writing

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Solution Overview

Problem

Conventional semiconductor memory devices require longer times for data writing due to inefficiencies in voltage management during the writing process.

Innovation Solution

The semiconductor memory device incorporates a memory cell with a gate electrode divided into a selection gate and a memory gate, along with specific sections for pulling out, discharging, and charging current to efficiently manage bit line voltage during data writing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional voltage management is used during writing, then the writing process is simpler, but the time required for data writing increases

Engineering Contradiction:
Improvewriting timeVSAvoidvoltage management structure
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The voltage management function is segmented into three distinct parts: pull-out part (lowers voltage by pulling out current), discharge part (lowers voltage by discharging), and charge part (applies voltage). This segmentation allows each part to be optimized for its specific function, enabling rapid voltage transitions while maintaining manageable overall complexity through clear functional separation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pull-out part operates in advance during the writing process to pull out current flowing from source to drain, proactively lowering the bit line voltage before the writing operation completes. This preliminary action prevents voltage buildup that would otherwise extend the writing time, thereby reducing total writing time without requiring complete redesign of the voltage management system.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the bit line voltage is lowered and applied rapidly, then the writing efficiency increases, but the control complexity increases

Engineering Contradiction:
Improvewriting efficiencyVSAvoidcontrol structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The voltage management system is made dynamic by enabling the pull-out part, discharge part, and charge part to be activated in different sequences depending on the writing phase. The control part dynamically switches between these parts: activating the pull-out part during writing, and switching to discharge/charge parts for voltage stabilization, thereby achieving rapid voltage transitions with adaptive control that manages complexity through flexibility.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The control part acts as an intermediary that coordinates between the multiple voltage management parts (pull-out, discharge, charge) and the memory cell. It receives writing commands and translates them into appropriate activation sequences of the voltage parts, simplifying the overall control by providing a single coordination layer that manages the complexity of switching between multiple voltage control mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250087273A1Semiconductor-memory device
Publication Date: 2025.03.13 RENESAS ELECTRONICS CORP
  • US20250087273A1 patent drawing
  • US20250087273A1 patent drawing
  • US20250087273A1 patent drawing

AI summary

To reduce the time required for data writing. A semiconductor memory device is provided, comprising a memory cell having a gate electrode including a selection gate and a memory gate, a source line connected to a source, and a bit line connected to a drain, an extraction part that extracts a current flowing from the source side to the drain side during writing in the memory cell from the bit line, a discharge part that has a higher ability to pass current than the extraction part and lowers the voltage of the bit line, a charge part that has a higher ability to pass current than the discharge part and applies a voltage to the bit line, and a control part that, when starting to write to the memory cell, lowers the voltage of the bit line by the discharge part and applies a voltage to the bit line by the charge part.