Memory Bit Cell Selection Logic for Low-Power Programming
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Solution Overview
Problem
Non-volatile memory devices, particularly one-time-programmable memory, face significant power consumption issues during programming due to the unnecessary activation of entire rows and columns of memory bit cells.
Innovation Solution
Incorporating a logic gate into each memory bit cell and utilizing second word lines oriented substantially perpendicular to bit lines and parallel to word lines, allowing for individual selection and programming of memory bit cells without activating entire rows or columns, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional row and column activation method is used for memory programming, then entire rows and columns are activated to ensure reliable programming, but power consumption increases significantly
Solution Approach 1:
The patent divides the memory array into smaller selectable units by introducing bit selection lines that can individually address specific memory bit cells within a row or column. This segmentation allows only the necessary bit cells to be activated during programming operations, rather than activating entire rows or columns, thereby reducing power consumption while maintaining programming reliability for the selected cells.
2Use of energy by moving object
If individual memory bit cell selection is implemented, then power consumption is reduced by activating only necessary cells, but device complexity increases due to additional logic gates and selection circuits
Solution Approach 1:
The patent combines the bit selection functionality with the existing row and column selection mechanisms by integrating bit selection lines and logic gates into the memory cell structure. This merging approach allows individual bit cell selection to be achieved without completely redesigning the memory architecture, as the bit selection lines work in conjunction with the existing row/column decoders and word/bit line structures.
3Loss of energy
If logic gates are added to each memory bit cell for individual selection, then capacitive loading is reduced by limiting activation to selected cells, but manufacturing complexity increases
Solution Approach 1:
The patent applies logic gates and bit selection circuitry locally only to the specific memory bit cells that require individual selection, rather than uniformly across the entire memory array. This local quality approach allows capacitive loading to be reduced in the selected regions while minimizing the overall impact on manufacturing complexity, as not all cells need to incorporate the additional selection logic.
Data Source
AI summary
Systems, devices, and methods are described herein for a programmable memory array. A programmable memory system includes an array of programmable memory bit cells. A memory bit cell of the array includes a first transistor of a first type controlled by a bit line, a second transistor of a second type responsive to a first word line and a second word line via a logic gate, and a third transistor of the second type responsive to the word line. The first word line is positioned substantially perpendicular to the bit line, and the second word line is positioned substantially parallel to the bit line. The first word line is activated via an X portion of an address. While the second word line is activated via a Y portion of the address.