Memory Bit-Line Segmentation via Plugs for Faster Pre-Charge
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Solution Overview
Problem
Memory devices face increased load on bit-lines during pre-charge and discharge operations, which hinders operation speed and efficiency.
Innovation Solution
The implementation of a memory device design where page buffers are coupled to bit-lines via plugs, allowing for reduced load distribution along the bit-lines, thereby shortening pre-charge and discharge times by dividing the bit-line length into smaller segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If page buffers are coupled directly to bit-lines, then the connection is simple, but the load on bit-lines increases and pre-charge time increases
Solution Approach 1:
The bit-line is divided into multiple segments by introducing plugs that create intermediate connection points. Each segment between plugs can be independently pre-charged, reducing the overall pre-charge time compared to a single long bit-line connection.
2Loss of time
If page buffers are coupled to the middle of bit-lines via plugs, then the load on bit-lines is reduced and pre-charge time decreases, but the device structure becomes more complex
Solution Approach 1:
Plugs are introduced as intermediary elements between the page buffers and bit-lines. These plugs serve as intermediate connection points that reduce the effective length of bit-line segments requiring pre-charge, thereby reducing pre-charge time while maintaining manageable structural complexity through standardized plug implementation.
3Area of stationary object
If bit-lines are made longer to connect page buffers, then the connection coverage is improved, but the load on bit-lines increases and operation speed decreases
Solution Approach 1:
The long bit-line is segmented into shorter effective segments by placing plugs at intermediate positions. This allows the page buffers to access a broader area (improved coverage) while each segment maintains shorter length for faster operation speed and reduced load.
Data Source
AI summary
The present disclosure may provide a memory device including a page buffer and bit-lines coupled thereto with a less load of the bit-lines. In one aspect of the present disclosure, there is provided a memory device comprising: bit-lines, each bit-line having opposite first and second ends; plugs coupled respectively to the bit-lines, each plug disposed between and excluding the first and second ends; and a page buffer coupled to the plugs.