Memory Device Blind Voltage Verify Start Time Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in efficiently performing verify operations across multiple program levels, leading to suboptimal programming times and potential data loss due to unreadable states.
Innovation Solution
The memory device incorporates a control logic circuit that applies a series of blind voltages related to a target program level to the word line, allowing for the determination of the start time point of a verify operation for the next program level based on the number of fail bits for each blind voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional verify operations are performed at each program level, then data accuracy is maintained, but programming time increases significantly
Solution Approach 1:
The patent applies preliminary action by performing a verify operation in advance at a first program level before completing programming at subsequent program levels. This early verification allows the system to detect potential programming failures early, and based on the verify result, dynamically adjust the programming strategy - either continuing with normal multi-level programming or switching to a simplified single-level programming mode, thereby optimizing overall programming time while maintaining data accuracy.
2Productivity
If verify operations are delayed until all program levels are complete, then programming speed is maximized, but data loss risk increases due to unreadable states
Solution Approach 1:
The patent implements feedback by using the verify operation result at the first program level to dynamically control the subsequent programming process. The verify result provides feedback that determines whether to continue with multi-level programming or switch to single-level programming, ensuring that programming operations proceed only when memory cells are in a readable state, thus preventing data loss while optimizing programming speed.
3Measurement precision
If blind voltages are applied to determine start time points, then verify operation timing precision is improved, but control circuit complexity increases
Solution Approach 1:
The patent applies parameter changes by using blind voltages with different voltage levels to determine the start time points of verify operations at different program levels. By varying the voltage parameters of blind voltages applied to the word line, the control logic circuit can precisely determine when to start verify operations based on the number of fail bits, achieving high timing precision without requiring complex external timing circuits.
Data Source
AI summary
A memory device includes a memory block including memory cells to which a program voltage is applied through a word line. The memory device also includes a peripheral circuit configured to perform a verify operation of comparing threshold voltages of the memory cells with a verify voltage on each of a plurality of program levels. The memory device further includes a control logic circuit configured to control the peripheral circuit to apply a plurality of blind voltages related to a target level among the plurality of program levels to the word line, and determine a start time point of a verify operation corresponding to a next program level of the target level using the number of fail bits for each of the plurality of blind voltages.