Semiconductor Memory Block Decoder Bad Block Sensing
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently determining whether a block is a bad block during memory cell array access, leading to increased access times and potential unintentional current flow.
Innovation Solution
The semiconductor memory device incorporates a block decoder with a sense node and a control unit that determines the state of a latch circuit based on the voltage of the sense node, allowing for efficient bad block sensing within the memory cell array access period by sharing paths for setting, resetting, and sensing the bad block latch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a separate bad block sensing operation is performed outside the memory cell array access period, then the latch circuit state can be determined accurately, but the access time increases
Solution Approach 1:
The patent merges the bad block sensing operation with the memory cell array access operation by sharing the bit line and latch circuit. The sense node voltage is evaluated during the normal read access period, combining two functions (data reading and bad block detection) into a single time window, thereby eliminating the need for a separate sensing operation.
Solution Approach 2:
The bit line and latch circuit are designed to serve dual purposes: normal data read operations and bad block detection. The same hardware resources are utilized for both functions, allowing the system to perform bad block sensing without dedicating separate time or resources, thus improving access time while maintaining sensing capability.
2Reliability
If separate paths for setting, resetting, and sensing the bad block latch are implemented, then the latch circuit state can be controlled precisely, but the circuit area increases
Solution Approach 1:
The patent combines the setting, resetting, and sensing functions into a single integrated path using the existing bit line and latch circuit infrastructure. Control signals are managed through the same hardware resources used for normal read operations, eliminating the need for separate dedicated paths and reducing circuit area while maintaining precise control over the latch state.
Solution Approach 2:
The latch circuit and associated control paths are designed to handle multiple functions (setting, resetting, sensing) through a unified structure. The same physical resources are reused for different control operations, reducing the overall circuit area while ensuring reliable and precise latch state management through proper signal timing and control logic.
3Loss of time
If the sense node voltage is evaluated during the memory cell array access period, then access time is reduced, but unintentional current flow may occur
Solution Approach 1:
The patent dynamically controls the evaluation of sense node voltage based on the state of the latch circuit. The sensing operation is conditionally performed only when the latch is in a specific state, allowing the system to adapt the sensing timing and avoid situations that would cause unintentional current flow, while still operating within the memory cell array access period.
Solution Approach 2:
The system uses feedback from the latch circuit state to control the sensing operation. The latch state information is used to determine whether and how to evaluate the sense node voltage, ensuring that sensing is performed only under conditions that prevent harmful current flow, thus resolving the contradiction between speed and safety.
Data Source
AI summary
A semiconductor memory device includes a block decoder having a sense node, and a control unit. The block decoder includes first and second transistors each connected between a first node and ground, a third transistor connected between a power source voltage and a second node, a fourth transistor connected between the first and second nodes and controlled by the same gate signal as the third transistor, a fifth transistor having a first terminal connected to the sense node and a gate connected to the second node through an inverter, and a latch circuit that switches the first transistor on and off according to its setting. The control unit determines the setting of the latch circuit, according to a logic level based on a voltage of the sense node during an operation in which the second and third transistors are turned off and the fourth transistor is turned on.