Nonvolatile Memory Block Erase Accuracy via GIDL Current Control
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Solution Overview
Problem
Conventional semiconductor memory devices face inaccuracies in erase operations due to leak currents flowing into memory cells from various wirings, leading to potential incorrect data erasure.
Innovation Solution
A nonvolatile semiconductor memory device configuration featuring a memory cell array with memory transistors arranged in a three-dimensional matrix, including a diode and select transistors, where the control circuit manages voltages to generate a GIDL current for accurate erase operations in selected memory blocks while preventing it in unselected blocks, using a diode to suppress leak currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an erase operation is executed on a semiconductor memory device with three-dimensionally disposed memory cells, then the memory cells can be erased, but leak current flows into the memory cells from various wirings causing inaccurate erase operations
Solution Approach 1:
The memory device is divided into multiple memory blocks, each independently erasable. The erase operation is segmented to affect only selected blocks while protecting others through controlled voltage application to word lines and bit lines, preventing leak current from causing unintended erasure in unselected blocks.
Solution Approach 2:
Select transistors are introduced as intermediary components between the word lines/bit lines and the memory cells. These select transistors act as gates that control current flow, allowing the erase operation to be precisely targeted at specific memory blocks while blocking leak current from reaching unselected blocks.
2Quantity of substance
If memory cells are disposed three-dimensionally to increase integration degree, then storage capacity increases, but leak current paths from wirings to memory cells increase
Solution Approach 1:
The three-dimensional memory array is segmented into multiple independent memory blocks. This segmentation allows selective erasure operations where only targeted blocks undergo the erase process, while other blocks are protected by maintaining their select transistors in the off state, thereby blocking leak current paths even in high-density 3D configurations.
Solution Approach 2:
The select transistors serve as intermediary control elements that manage current flow to three-dimensionally arranged memory cells. By controlling the gate voltages of these select transistors, the invention enables precise routing of erase currents to specific memory blocks while preventing leak current from affecting other blocks, thus managing the increased complexity of current paths in 3D memory structures.
3Productivity
If voltage is applied to perform erase operation, then data erasure is achieved, but incorrect erase operations may occur in unselected memory blocks
Solution Approach 1:
The erase operation is segmented by applying different voltage levels to different word lines and bit lines corresponding to different memory blocks. Selected memory blocks receive the full erase voltage, while unselected blocks receive reduced or zero voltage, ensuring that the high-speed erase operation affects only the intended blocks and maintains precise targeting accuracy.
Solution Approach 2:
The select transistors act as voltage-controlled intermediaries that regulate the application of erase voltages. By setting appropriate gate voltages on the select transistors, the invention enables the rapid application of erase voltages to selected blocks while simultaneously blocking voltage application to unselected blocks, thus achieving both high productivity and precise targeting accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures precise data erasure by controlling voltage differences across memory blocks, preventing incorrect erase operations and maintaining the integrity of unselected memory blocks.
Implementation Method 1
the control circuit is configured to perform an erase operation on a selected one of the plurality of memory blocks by controlling a voltage difference between a bit line and a gate of a select transistor to generate a GIDL current
Implementation Method 2
using a diode to suppress leak currents
Data Source
AI summary
A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.