Memory Block Erase Sub-Operations During Program
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Solution Overview
Problem
Current memory devices face inefficiencies in transitioning between memory blocks during program operations, particularly in the time required to perform erase operations on subsequent blocks, which affects overall system performance and efficiency.
Innovation Solution
A memory device and system architecture that allows for sub-operations of erase operations to be performed on subsequent blocks during program operations on current blocks, utilizing incremental step pulse erase (ISPE) methods with multiple erase voltage groups, enabling efficient switching between blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory device waits to perform erase operations until after program operations are completed, then the program operation can proceed without interruption, but the total operation time increases due to sequential execution
Solution Approach 1:
The patent performs preliminary actions by executing sub-operations of the erase operation on the subsequent open block during the program operation on the current open block. This preliminary execution of erase sub-operations (such as threshold voltage adjustment and charge removal) prepares the subsequent block in advance, so that when it becomes the current block, the remaining erase operations can be completed more quickly, thereby reducing the overall loss of time without interrupting the program operation.
2Reliability
If the memory device performs complete erase operations before program operations, then data integrity is ensured, but the transition time between blocks increases
Solution Approach 1:
The patent segments the erase operation into multiple sub-operations that can be executed at different stages. The first sub-operations are performed during the program operation on the current block to prepare the subsequent block, while the second sub-operations are completed after the program operation. This segmentation allows the erase process to be distributed across different time periods, ensuring data integrity through complete execution while reducing the concentrated transition time between blocks.
Solution Approach 2:
The patent maintains continuity of useful action by overlapping the execution of program operations on the current block with the execution of erase sub-operations on the subsequent block. This continuous utilization of processing resources ensures that both operations make progress simultaneously, preventing idle time and maintaining productive work throughout the block transition process, thereby reducing overall operation time while preserving data integrity.
Data Source
AI summary
Provided herein may be a memory device, a memory system including the memory device, and a method of operating the memory system. The memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to perform a program operation and an erase operation on any of the plurality of memory blocks; and a logic group configured to control the peripheral circuit to perform the program operation and the erase operation. The logic group may control the peripheral circuit to perform, during the program operation on a first memory block, selected as a current open block among the plurality of memory blocks, sub-operations of an erase operation on a second memory block to be selected as a subsequent open block.