Non-Volatile Memory Block Erase Voltage Segmentation

Solution Overview

Problem

In non-volatile memory systems, the existing erase operations uniformly apply voltage to entire memory blocks, leading to a 'deep erase' condition that skews the erased state of unprogrammed memory cells, affecting efficiency, reliability, and power consumption.

Innovation Solution

Applying an erase voltage bias to the channel region of a partially programmed memory block, while applying a word line voltage to programmed word lines and omitting it for unprogrammed word lines to prevent skewing of the erased state.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If uniform erase voltage is applied to entire memory block, then erase operation is simplified, but deep erase condition occurs skewing erased state of unprogrammed cells

Engineering Contradiction:

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The memory block is segmented into programmed and unprogrammed regions. Different voltage levels are applied to different segments: higher erase voltage to programmed cells requiring erasure, and lower voltage to unprogrammed cells that should maintain their erased state. This segmentation prevents deep erase conditions in unprogrammed cells while effectively erasing programmed cells.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different voltage characteristics are applied to different spatial regions of the memory block based on their programming state. Programmed cells receive a higher erase voltage level, while unprogrammed cells receive a lower voltage level, creating local quality variations that prevent deep erase conditions in specific regions while maintaining effective erasure in others.

Inventive Principle:

Principle #3Local quality

2Productivity

If uniform erase voltage is applied to entire memory block, then processing is faster, but power consumption increases due to unnecessary erasure of unprogrammed cells

Engineering Contradiction:

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

Instead of applying full erase voltage uniformly across the entire memory block, the invention applies partial erase action only where needed (programmed cells) and reduced voltage where not needed (unprogrammed cells). This partial action approach maintains erase speed for programmed cells while reducing unnecessary power consumption in unprogrammed regions.

Inventive Principle:

Principle #16Partial or excessive action

3Device complexity

If uniform erase voltage is applied to entire memory block, then device complexity is reduced, but manufacturing precision requirements increase to handle deep erase conditions

Engineering Contradiction:

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The erase control circuitry is segmented to provide at least two distinct voltage levels: a first voltage level for programmed cells and a second voltage level for unprogrammed cells. This segmentation allows the system to maintain relatively simple device architecture while achieving precise voltage control through dedicated voltage generation circuits for each cell type.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures discrete and efficient erase operations, preventing 'deep erase' conditions and maintaining the integrity of unprogrammed memory cells' states, thereby enhancing the reliability and power efficiency of future programming/erase cycles.

Implementation Method 1

applying an erase voltage bias level to a channel region of the memory block, applying a word line voltage level to all programmed word line(s) of the memory block

Methodology Applied

Scientific EffectVoltage bias application: Electric Field

Data Source

PatentUS11901016B2Fast open block erase in non-volatile memory structures

Publication Date: 2024.02.13

AI summary

A method for performing an erase operation of a partially programmed memory block of a non-volatile memory structure. The method comprises: (1) applying an erase voltage bias level to a channel region of the memory block, (2) applying a word line voltage level to all programmed word line(s) of the memory block, (3) applying a “float” condition to all unprogrammed word line(s) of the memory block, and (4) applying an erase verify operation to all word line(s) of the memory block, wherein the “float” condition comprises omitting application of the word line voltage to the unprogrammed word line(s).