Memory Block Low-Stress Refresh Erase for Programming Disturbance Control
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Solution Overview
Problem
Conventional erase operations in non-volatile memory devices cause programming disturbances due to residual holes trapped in wordlines and channels, leading to threshold voltage shifts and read margin issues, which are exacerbated by immediate programming after erase operations, and existing methods to mitigate these disturbances are inefficient.
Innovation Solution
Implementing a low stress refresh erase process that includes a first erase operation followed by periodic erase detection, and if necessary, a second erase operation with reduced voltage magnitude and duration, omitting the pre-programming pulse to minimize residual hole trapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erase operations are performed with high voltage, then erase completeness is improved, but programming disturbances increase due to residual hole trapping
Solution Approach 1:
The erase operation is divided into two distinct phases: a initial erase operation followed by a refresh erase operation. This segmentation allows the system to first perform a complete erase with necessary voltage levels, then subsequently reduce voltage stress to minimize hole trapping while maintaining erase effectiveness through periodic verification.
Solution Approach 2:
The initial erase operation is performed as a preliminary action before the refresh erase. This preliminary high-voltage erase ensures complete erasure of the block, and subsequent periodic erase detection operations verify whether refresh erase is needed, allowing the system to perform low-stress erases only when necessary.
2Productivity
If immediate programming is performed after erase, then productivity is improved, but threshold voltage shifts occur due to residual holes
Solution Approach 1:
Periodic erase detection operations are performed after the initial erase to detect residual holes. This feedback mechanism allows the system to determine whether refresh erase operations are needed before programming, enabling immediate programming when conditions are favorable while maintaining threshold voltage stability when residual holes are present.
3Object-generated harmful factors
If refresh erase is performed periodically, then programming disturbances are reduced, but device complexity increases
Solution Approach 1:
The system performs self-verification through periodic erase detection operations that monitor the block's erase status. This self-service approach allows the memory device to automatically determine when refresh erase is needed without external intervention, managing the complexity internally while maintaining simple external interfaces.
Data Source
AI summary
A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.