Non-volatile Memory Block Segmentation for Leak Current Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current stacked non-volatile semiconductor memory devices face challenges in reducing leak current and improving read margin during memory operations, particularly due to complex circuit operations and limited storage capacity in high-density memory arrays.
Innovation Solution
The implementation of a non-volatile semiconductor memory device with a memory cell array configuration that includes multiple memory blocks sharing source lines, where selected and non-selected memory strings are supplied with distinct voltages to minimize leak current and simplify circuit operations, while maintaining efficient data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple memory blocks share source lines, then device area is reduced and circuit operations are simplified, but leak current increases and read margin deteriorates
Solution Approach 1:
The patent segments the memory device into multiple memory blocks (MB1, MB2, etc.) that can be independently controlled through separate block select lines (BLS0, BLS1, etc.). Each memory block contains multiple memory strings that share source lines, but the block-level segmentation allows independent voltage control to prevent leak current from affecting the entire device. This resolves the contradiction by maintaining area efficiency through source line sharing while using block segmentation to control leak current propagation.
Solution Approach 2:
The patent applies different voltage conditions to different regions of the memory device based on selection state. Selected memory blocks receive voltages that minimize leak current (e.g., VSL selected < VBL), while non-selected blocks are placed in high-impedance states. This local quality control allows source lines to be shared across multiple blocks without propagating leak current throughout the entire device, thereby maintaining both area efficiency and low leak current.
2Quantity of substance
If multiple memory blocks share source lines, then storage capacity increases, but read margin decreases due to increased leak current
Solution Approach 1:
By segmenting the memory device into independently controllable blocks with separate block select lines, the patent enables high storage capacity through multi-block operation while preventing leak current from degrading read margin across the entire device. The segmentation allows read operations to be confined to selected blocks only, isolating them from leak current effects in non-selected blocks.
Solution Approach 2:
The patent implements local quality control by applying specific voltage conditions only to selected memory blocks during read operations. Selected blocks receive optimized voltage combinations (e.g., VSL selected < VBL) that maximize read margin, while non-selected blocks are placed in high-impedance states. This localized voltage control maintains high storage capacity through multi-block sharing while preserving read margin in active blocks.
3Object-generated harmful factors
If complex voltage control strategies are implemented for selected and non-selected memory strings, then leak current is reduced and read margin is improved, but device complexity increases
Solution Approach 1:
The patent merges the control of multiple memory blocks into a unified architecture where block select lines (BLS0, BLS1, etc.) collectively manage all blocks. The source lines are shared resources that serve multiple blocks simultaneously, reducing the need for separate dedicated lines for each block. This merging approach reduces device complexity while maintaining the ability to implement voltage control strategies for leak current reduction.
Solution Approach 2:
The block select lines and source lines serve multiple functions: they simultaneously select and control multiple memory blocks, provide voltage control for leak current reduction, and enable hierarchical memory access. This multi-functionality reduces the overall number of control lines needed, simplifying the device architecture while maintaining complex voltage control capabilities for improving read margin and reducing leak current.
Data Source
AI summary
In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.