3D Memory Buffer Layer Reduces Charge Trapping
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits has led to increased complexity in processing and manufacturing, particularly in 3D memory devices, where challenges such as low mobility of poly-silicon channels and interfacial layers with low dielectric constants result in charge trapping and reliability issues, including endurance failure and threshold voltage shifts.
Innovation Solution
A 3D memory device is proposed with a buffer layer of high dielectric constant between the ferroelectric layer and the channel layer to reduce interfacial charge trapping, enhancing switchable performance, decreasing operation voltage, and increasing the operation window, thereby improving reliability and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a poly-silicon channel is used in 3D memory devices, then the device structure can be formed, but the channel mobility is low resulting in poor device performance
Solution Approach 1:
The patent changes the material parameter of the channel from poly-silicon to a different semiconductor material with superior mobility characteristics, directly addressing the low mobility issue while maintaining the 3D memory device structure
Solution Approach 2:
The patent introduces a composite structure with a buffer layer having high dielectric constant placed between the channel and ferroelectric layer, creating a composite material system that improves overall device performance by combining materials with complementary properties
2Reliability
If an interfacial layer with low dielectric constant is used between ferroelectric layer and channel, then the structure can be simplified, but charge trapping occurs resulting in reliability issues
Solution Approach 1:
The patent introduces a buffer layer as an intermediary between the ferroelectric layer and channel, with high dielectric constant properties that prevent charge trapping at the interface, thereby improving reliability without significantly complicating the overall structure
Solution Approach 2:
The patent changes the dielectric constant parameter of the interfacial layer from low to high by selecting appropriate buffer materials, which fundamentally alters the electrical characteristics at the interface to prevent charge trapping
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of a high dielectric constant buffer layer effectively decreases interfacial charge trapping, enhancing the switchable performance of the ferroelectric layer, reducing operation voltage, and increasing the reliability and endurance of the 3D memory device.
Implementation Method 1
A 3D memory device is proposed with a buffer layer of high dielectric constant between the ferroelectric layer and the channel layer to reduce interfacial charge trapping
Data Source
AI summary
Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.