Variable Resistance Memory Device With Buffer Layer
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Solution Overview
Problem
Current memory devices with cross-point structures face challenges in maintaining high endurance and reducing power consumption due to rapid increases in reset resistance over time, which affects their ability to store data reliably in high-resistance and low-resistance states.
Innovation Solution
The memory device incorporates a variable resistance memory layer and a buffer resistance layer connected in parallel, with the buffer resistance layer having a resistivity lower than the reset resistance state of the memory layer, which helps in maintaining a stable set resistance and reducing the increase rate of reset resistance, thereby improving endurance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a variable resistance memory layer is used in a cross-point structure memory device, then data storage capability is improved, but reset resistance increases rapidly over time affecting reliability
Solution Approach 1:
The memory device is divided into two separate resistance layers: a variable resistance memory layer for data storage and a buffer resistance layer for stabilizing resistance. This segmentation allows each layer to perform its specific function independently, with the buffer layer compensating for resistance drift in the memory layer over time.
Solution Approach 2:
The patent uses a composite structure combining two different resistance layers with distinct material properties. The variable resistance memory layer provides high resistance change ratio for data storage, while the buffer resistance layer provides stable resistance characteristics to counteract time-dependent drift, creating a composite system with superior overall performance.
2Quantity of substance
If the variable resistance memory layer has high resistance change ratio, then data storage density is improved, but power consumption increases
Solution Approach 1:
The buffer resistance layer acts as an intermediary element between the variable resistance memory layer and the read/write circuitry. It mediates the resistance changes by providing a stable reference that reduces the voltage and current required for reliable data detection, thereby lowering power consumption while maintaining high storage capacity.
Solution Approach 2:
The patent optimizes the resistance parameters of both layers: the variable resistance memory layer maintains high resistance change ratio for data storage, while the buffer resistance layer is designed with specific resistance values that reduce overall power consumption by improving the signal-to-noise ratio during read operations.
3Stability of the object's composition
If the buffer resistance layer has lower resistivity than reset state, then set resistance stability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent specifies precise resistivity parameter ranges for the buffer resistance layer (lower than the reset state resistance of the memory layer) to achieve optimal set resistance stability. These parameter specifications guide the manufacturing process and material selection, enabling consistent performance while managing manufacturing complexity through clear design criteria.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for improved endurance and reduced power consumption by maintaining stable resistance states, enabling efficient storage of data in both high-resistance and low-resistance states, thus enhancing the memory device's performance and reliability.
Implementation Method 1
Materials forming a variable resistance memory layer of the memory device having the cross-point structure may have resistance values changing according to an applied voltage
Implementation Method 2
the buffer resistance layer including a material having a resistivity that is less than a resistivity of the variable resistance memory layer in a high-resistance state and greater than a resistivity of the variable resistance memory layer in a low-resistance state
Data Source
AI summary
A memory device including a first conductive line on a substrate and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction that is perpendicular to the first horizontal direction; and a memory cell between the first conductive line and the second conductive line, the memory cell including a variable resistance memory layer, a buffer resistance layer, and a switch material pattern, extending in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction, and having a tapered shape with a decreasing horizontal width along the vertical direction, wherein at least a part of the variable resistance memory layer and at least a part of the buffer resistance layer of the memory cell are at a same vertical level.