Memory Device With Buried Gate And High-k Dielectric
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Solution Overview
Problem
The integration of memory and MOS transistors into a single chip is costly and complex due to separate fabrication processes, increasing production costs and reducing competitiveness.
Innovation Solution
A memory device is fabricated simultaneously with a metal gate process, incorporating a buried floating gate, a control gate formed at the same level as the metal gate, and a high-k inter-gate dielectric layer, allowing for the integration of memory and MOS transistors with reduced process complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate fabrication processes are used for memory and MOS transistors, then functional integration is achieved, but process complexity and cost increase
Solution Approach 1:
The patent merges the memory fabrication process with the MOS transistor fabrication process by using a unified multi-layer gate structure. The control gate and floating gate are integrated into a single device architecture, allowing both memory and transistor functions to be fabricated simultaneously using the same high-k metal gate process, thereby reducing process complexity while maintaining functional integration
Solution Approach 2:
The unified gate structure serves multiple functions: the control gate enables MOS transistor operation, while the floating gate provides memory storage capability. This multi-functional design allows a single fabrication process to produce both memory and transistor elements, eliminating the need for separate fabrication processes
2Adaptability or versatility
If separate fabrication processes are used for memory and MOS transistors, then functional integration is achieved, but manufacturing cost increases
Solution Approach 1:
By combining memory and MOS transistor fabrication into a single unified process using the high-k metal gate structure, the patent eliminates redundant fabrication steps, reduces the number of photo-masks required, and decreases manufacturing complexity, thereby significantly reducing production costs while achieving functional integration
3Device complexity
If control gate is formed at the same level as metal gate, then process simplification is achieved, but control gate damage during polishing may occur
Solution Approach 1:
The patent employs a composite gate structure where the control gate is formed with metal material at the same level as the high-k metal gate. This composite design allows the control gate to be integrated into the metal gate process flow, and through optimized polishing procedures, the control gate maintains its integrity while enabling process simplification
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous integration of memory and MOS transistors with the existing high-k and metal gate process, reducing process costs and improving competitiveness by avoiding damage to the control gate during polishing and simplifying the fabrication process.
Implementation Method 1
the inter-gate dielectric layer includes a high-k layer having a dielectric constant of greater than about 10
Data Source
AI summary
Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. The inter-gate dielectric layer comprises a high-k layer having a dielectric constant of greater than about 10.