Memory Bus Broadcast for Data Processor Units
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Solution Overview
Problem
Parallel processing in data processors is hindered by long routing times and inefficient use of memory space due to the need for dedicated broadcast buses, which increases complexity and reduces marginal increases in operating speeds.
Innovation Solution
Eliminating the need for a dedicated broadcast bus by using existing memory buses to transmit data from a controller to processor units, thereby reducing chip real estate and improving performance by reusing existing hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a dedicated broadcast bus is used to transmit data to all processor units, then data can be transmitted to all processor units simultaneously, but the routing time becomes long and the device complexity increases
Solution Approach 1:
The patent combines the broadcast bus functionality with the existing memory data bus. Instead of having a separate dedicated broadcast bus, the memory data bus is used to transmit broadcast data to all processor units. This merging eliminates the need for additional routing lines and reduces device complexity while maintaining the ability to transmit data simultaneously to all processor units.
Solution Approach 2:
The memory data bus is given multiple functions: it serves both as the data bus for memory operations and as the broadcast bus for transmitting data to all processor units. This multi-functionality eliminates the need for a dedicated broadcast bus, reducing routing complexity and device complexity while maintaining fast data transmission capability.
2Ease of operation
If constants are stored in each computational unit's memory space, then broadcast data can be stored locally, but a great deal of memory space is wasted
Solution Approach 1:
The patent merges the broadcast data storage function with the main memory. Instead of having separate local storage for constants in each computational unit, the memory system is used to store broadcast data. This eliminates wasted memory space while maintaining local access capability, as the memory is efficiently shared across all processor units.
Solution Approach 2:
The memory system serves multiple purposes: it stores both operational data and broadcast constants. By making the memory universal and shared across all processor units, the system eliminates the need for duplicate constant storage in each unit, optimizing memory space utilization while maintaining ease of access to broadcast data.
3Speed
If more routing lines are added to connect the broadcast bus to computational units, then data can be transmitted faster, but the device complexity and chip area increase
Solution Approach 1:
The patent merges the broadcast routing function with the existing memory data bus infrastructure. By using the same physical bus lines for both memory operations and broadcast data transmission, the system achieves fast data transmission without adding more routing lines, thereby avoiding increased chip area and device complexity.
Solution Approach 2:
The memory data bus is designed to be universal, handling both memory data transfer and broadcast data transmission. This multi-functionality eliminates the need for additional dedicated broadcast routing lines, maintaining fast transmission speeds while minimizing chip area usage by reusing existing hardware resources.
Data Source
AI summary
A data processor apparatus and memory interface comprises a memory, a plurality of processor units couplable to receive data from the memory, and control means for controlling transmission of data from the control means to each processor unit. The control means for controlling operations of the data processor units is arranged to transmit data intended for each processor unit (i.e. broadcast data) to the memory, and is adapted to control each processor unit to receive the broadcast data from the memory. This arrangement eliminates the need for a dedicated broadcast bus from the array controller to each PU, which thereby enables the area/space required to accommodate the data processor to be significantly reduced.