Multi-Port Memory Bypass Path for At-Speed Transition Fault Testing
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Solution Overview
Problem
Existing testing methods for integrated circuits, particularly those with multi-port and multi-clock memories, struggle to effectively cover at-speed transition faults and transient faults in shadow logic circuits, especially when programmable non-logic circuits operate asynchronously in read and write modes.
Innovation Solution
Implementing a multiplexer circuit in the input/output paths of memory circuits, controlled by a test bypass signal, to enable at-speed transition fault testing by synchronizing the testing path with the read clock domain, and using a bypass path to isolate the memory from the testing process, allowing for synchronized fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If BIST mechanisms are used for testing memory circuits, then memory testing coverage is improved, but testing coverage of surrounding digital logic circuits (shadow logic) deteriorates
Solution Approach 1:
The testing mechanism is designed to serve multiple functions: it can test both the memory circuit itself (through BIST modes) and the surrounding shadow logic circuits (through scan chain and bypass path modes). The multiplexer circuit and bypass path enable the same testing infrastructure to adaptively switch between testing memory and testing shadow logic, achieving universal testing capability without requiring separate dedicated testing systems for each component.
2Adaptability or versatility
If scan chain testing mechanisms are used for testing digital logic circuits, then shadow logic testing is improved, but at-speed transition fault testing deteriorates
Solution Approach 1:
The testing system dynamically switches between different operational modes (BIST mode, scan chain mode, and bypass path mode) based on the testing objectives. The multiplexer circuit enables dynamic reconfiguration of the testing path, allowing the system to transition from slow scan chain testing to fast at-speed transition fault testing by selecting appropriate data paths and clock domains for the specific test being performed.
3Adaptability or versatility
If memory circuits operate asynchronously in read and write modes, then operational flexibility is improved, but testing complexity deteriorates
Solution Approach 1:
The bypass path acts as an intermediary that decouples the testing process from the memory's internal asynchronous operations. By providing a direct test data path that bypasses the memory array and uses the read clock domain independently of write operations, the system can test shadow logic without being constrained by the memory's asynchronous read-write timing requirements, thereby simplifying the testing complexity while preserving operational flexibility.
Data Source
AI summary
A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.