Nonvolatile Memory Cache Read Voltage Update Mechanism
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Solution Overview
Problem
Existing nonvolatile memory devices face challenges in efficiently performing cache read operations, particularly in changing read voltages during operations, which affects the speed and efficiency of data retrieval in multi-level cell programming.
Innovation Solution
A nonvolatile memory device with first and second registers and a microcontroller that allows for dynamic parameter management, enabling the storage and application of new read voltages during cache read operations by distinguishing between internal and external operations through a flag system, allowing for efficient parameter changes even during ongoing cache read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a cache read method is used to reduce read operation time, then read speed is improved, but the ability to change read voltage during operation deteriorates
Solution Approach 1:
The patent divides the parameter storage function into two separate registers: a first register for storing parameters during idle periods and a second register for storing parameters during cache read operations. This segmentation allows the system to maintain both fast cache read capability and the ability to update parameters without conflict, as each register serves a specific operational state.
Solution Approach 2:
The patent implements preliminary action by storing updated read voltage parameters in the second register before they are needed during cache read operations. The control logic unit prepares the parameters in advance during idle periods or when update commands are received, ensuring that when a cache read operation begins, the correct parameters are already ready for immediate use without interrupting the operation.
2Adaptability or versatility
If parameters are updated during ongoing cache read operations, then adaptability is improved, but system complexity deteriorates
Solution Approach 1:
The patent introduces a control logic unit as an intermediary between the parameter update commands and the register storage system. This intermediary manages the complexity by automatically determining whether to store parameters in the first or second register based on the current operational state, thereby shielding the rest of the system from the complexity of parameter management while enabling flexible updates.
3Adaptability or versatility
If two registers are used for parameter storage, then parameter management flexibility is improved, but device complexity deteriorates
Solution Approach 1:
The patent merges the functionality of parameter storage and operation state tracking into a unified control logic unit that manages both the first and second registers. This merging approach reduces overall system complexity by consolidating control functions rather than requiring separate management mechanisms for each register, while still providing the flexibility of dual-register storage for different operational states.
Data Source
AI summary
A nonvolatile memory device includes first and second registers configured to store parameters received via an input/output (IO) unit, a microcontroller configured to control an operation of the nonvolatile memory device according to the parameter stored in the first register, and a control logic unit configured to, when a parameter is received via the IO unit while the microcontroller performs an internal operation, store the received parameter in the second register.