Memory Calibration Circuitry for Neural Network Accuracy
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Solution Overview
Problem
Conventional memory arrays in learning/inference machines, such as those used in deep convolutional neural networks, face inefficiencies in memory utilization due to varying data sets, leading to suboptimal aspect ratio utilization and potential accuracy losses from limited voltage head-room and sense amplifier offsets.
Innovation Solution
The implementation of a memory array with configurable multiplexers and sensing circuits that employ calibration control circuitry to compensate for sense amplifier offsets and optimize data storage through distributed calibration information, allowing for efficient data processing across varying compute clusters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional memory arrays are used with fixed sensing circuits, then manufacturing is simpler, but accuracy is reduced due to sense amplifier offsets
Solution Approach 1:
The patent applies preliminary action by performing calibration of sense amplifier offsets before actual data processing operations. Calibration values are pre-computed and stored in the memory array, so that when data processing occurs, the previously determined calibration information is used to compensate for offsets, thereby improving accuracy without adding complexity to the main processing path
Solution Approach 2:
The patent introduces calibration control circuitry as an intermediary component that mediates between the sensing circuits and the data processing operations. This intermediary circuitry manages the calibration process, stores calibration values, and applies corrections, effectively isolating the complexity of offset compensation from both the sensing circuits and the main processing logic
2Productivity
If memory arrays optimize for square aspect ratio, then manufacturing is easier, but efficiency is reduced when processing varying data sets
Solution Approach 1:
The patent applies dynamics by making the memory array's operational configuration adaptive rather than fixed. The system can dynamically adjust its effective aspect ratio and data storage configuration based on the specific data set being processed, allowing optimization for different compute cluster sizes and data dimensions without requiring physical reconfiguration of the memory array itself
Solution Approach 2:
The patent utilizes parameter changes by allowing the memory array to change its operational parameters such as word line activation patterns, bit line grouping, and sense amplifier allocation based on the input data characteristics. This enables the same physical memory array to efficiently handle varying data sets with different aspect ratios and compute cluster requirements
3Measurement precision
If sense amplifiers operate with limited voltage head-room, then power consumption is reduced, but accuracy is lost due to offsets
Solution Approach 1:
The patent extracts the offset error component from the sensing operation by separately measuring and storing calibration values that represent the offset. This extracted offset information is then used to correct subsequent measurements, allowing the sense amplifiers to operate with limited voltage head-room without sacrificing accuracy, as the offset correction is applied in software/firmware rather than requiring additional voltage margin
Data Source
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AI summary
A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values. The stored data values may be stored in an in-memory compute cluster of the memory array, such that operations on the stored data values include combining the multiple data values of the in-memory compute cluster with at least a portion of the generated calibration information as at least part of an in-memory compute operation for the in-memory compute cluster.